Altera Shift Register IP Core User Manual
Lpm_shiftreg megafunction, Features, General description
Table of contents
Document Outline
- LPM_SHIFTREG Megafunction
- Features
- General Description
- Device Family Support
- Resource Utilization
- Customizing Megafunctions in the GUI
- Infer Megafunctions from HDL Code
- Instantiate Megafunctions in HDL Code
- Simulating Megafunctions
- Debugging with the SignalTap II Embedded Logic Analyzer
- Design Example: Configurable 8Bit SIPO or PISO Shift Register
- Design Example: Time Delay
- Ports and Parameters
- Revision History