Altera Shift Register IP Core - Manual

LPM_SHIFTREG Megafunction
2013.03.05
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This document describes the Altera ® -provided megafunction IP core optimized for Altera ® device
architectures. Using megafunctions instead of coding your own logic saves valuable design time, offering
more efficient logic synthesis and device implementation. Scale the megafunction's size by simply setting
parameters.
Features
The LPM_SHIFTREG megafunction implements a shift register and offers many additional features, including:
• Synchronous or asynchronous inputs to shift register
• Synchronous parallel load
• Left/right register shifting
• Optional inputs, including clock enable input, serial shift data input, and parallel input
• Optional outputs, including data output and serial shift data output
General Description
The LPM_SHIFTREG megafunction is a memory compilation IP core accessible from the Quartus II ®
MegaWizard ® Plug-In Manager.
Shift registers are a type of sequential logic circuit, that mainly store digital data. These cores are comprised
of a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the
next flip-flop. All the flip-flops are driven by a common clock and are set or reset simultaneously. A shift
register is useful for converting parallel signals to serial signals and vice versa. Most of the registers possess
no characteristic internal sequence of states.
The shift register megafunction is highly parameterizable block of logic. You can use this megafunction to
implement long delay chains. The megafunction provides for either left shift or right shift of the input data
bits. Shifted data is either loaded in parallel into the registers synchronously, or in serial through the shiftin
input of the megafunction. The loaded data is then shifted with the rising edge of clock input.
The shift operation is a single clock-edge operation with an active-high clock enable feature. When enable
is High, the input (D) is loaded into the first bit of the shift register, and each bit is shifted to the next highest
bit position. Cascading of shift registers is another way of using the LPM_SHIFTREG megafunction to
achieve higher shift count or bit count.
Optional inputs are available to asynchronously clear or set the registers, or synchronously clear or set the
registers. Using this feature, you can either set the initial value of all the registers to 1, or to a desired value.
Parallel output q[] is used to read parallel data from the shift register. Parallel data is always available on
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