Altera Shift Register IP Core - Manual (Page 10)

The support page has links to topics such as installation, usage, and troubleshooting.
Set up the ModelSim-Altera simulator by performing the following steps:
1. Unzip the lpm_shiftreg_ex1_msim.zip file to any working directory on your PC.
2. Start Modelsim-Altera
3. On the File menu, click Change Directory.
4. Select the folder in which you unzipped the files. Click OK.
5. On the Tools menu, click Execute Macro.
6. Select the
shiftreg_ex1.do file and click Open.
This is a script file for ModelSim that automates all necessary settings for the simulation. Note:
You can rearrange signals, remove signals, add signals and change the radix by modifying the script in
shiftreg_ex1.do accordingly to adjust the results in your preferred simulator.
Design Example: Time Delay
This design example uses the LPM_SHIFTREG megafunction to implement time delay functionality. In this
example you implement a time delay with the LPM_SHIFTREG megafunction.
• Generating a time delay module.
• Implement design and assign the 5SGMD4E1H29C1 Stratix V GS device to the project.
• Compile and simulate the design.
Design Files
The design files are available in the Quartus II Projects section on the Design Examples page of the Altera
web site: Select the “Examples for lpm_shiftreg Megafunction User Guide” link from the examples page to
download the design files.
Related Information
Design Examples
Generating the Time Delay Design
To build and configure the LPM_SHIFTREG megafunction with the time delay design example, perform
the following steps:
1. In the Quartus II software, open the lpm_shiftreg_DesignExample__ex2.qar project.
2. On the Tools menu, click. MegaWizard Plug-In Manager.
3. On page 1 of the MegaWizard Plug-In Manager, select Create a new custom megafunction variation,
and click Next.
4. On Page 2a of the MegaWizard Plug-In Manager, select Stratix V from the Which device family will
you be using? list.
5. Click Verilog HDL under Which type of output file do you want to create?.
6. Expand the Memory Compiler folder and select LPM_SHIFTREG. Specify the output file
shiftreg_ex2 .
7. Click Next.
8. On Page 3, set the width of the output bus in the How wide should the ‘q’ output bus be? list to 8.
9. Under What direction do you want the registers to shift?, select Left.
LPM_SHIFTREG Megafunction Altera Corporation
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Design Example: Time Delay 10
2013.03.05