Altera PowerPlay Early Power Estimator - Manual (Page 23)

Altera Corporation 3–7
October 2005 PowerPlay Early Power Estimator User Guide: Stratix, Stratix GX & Cyclone FPGAs
Using PowerPlay Early Power Estimator for Stratix, Stratix GX & Cyclone FPGAs
Figure 3–5. TFF Example
Figure 3–6. 4-Bit Counter Example
Figure 3–7 shows the Resource Usage Summary in the Quartus II
software Compilation Report for a design targeting the Stratix device
family. The Compilation Report provides the total number of LEs used by
the design and the average fan-out. You can view the Fitter Resource
Utilization by Entity
section of the Compilation Report or use the
Hierarchies tab of the Project Navigator to determine how many LEs are
in each entity. Using this information from the Compilation Report, you
can enter in the appropriate information into the PowerPlay early power
estimator.
Figure 3–8 shows the Stratix device PowerPlay early power
estimator and the estimated power consumed by the LEs in this design.
PRN
CLRN
T Q
TFF
clock
V
CC
INPUT
V
CC
OUTPUT
tff output
PRN
CLRN
T Q
TFF
PRN
CLRN
T Q
TFF
PRN
CLRN
T Q
TFF
PRN
CLRN
T Q
TFF
V
CC
V
CC
V
CC
V
CC
cout2 cout1 cout0 clock
cout3
OUTPUT
cout0 cout0
OUTPUT
cout3 cout3
OUTPUT
cout2 cout2
OUTPUT
cout1 cout1