Estimating power before creating fpga design, Estimating power while creating the fpga design – Altera PowerPlay Early Power Estimator User Manual
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2–2 Chapter 2: Setting Up Cyclone III PowerPlay Early Power Estimator
Estimating Power
PowerPlay Early Power Estimator User Guide for Cyclone III FPGAs
© June 2009 Altera Corporation
Estimating Power Before Creating FPGA Design
FPGAs provide the convenience of a shorter design cycle and faster time-to-market
than ASICs or ASSPs. The board design often takes places during the FPGA design
cycle. Thus, the power planning for the device can happen before the FPGA design is
complete.
Table 2–1
shows the advantages and disadvantages of using the PowerPlay Early
Power Estimator before you begin the FPGA design.
Perform the following steps to estimate power usage with the PowerPlay Early Power
Estimator if you have not started your FPGA design:
1. Download the PowerPlay Early power Estimator from the Altera website on
page.
2. Select the target family and device package from the Device section of the
PowerPlay Early Power Estimator spreadsheet's.
3. Enter values in the fields on each section in the PowerPlay Early Power Estimator.
Different worksheets in the file display different power sections, such as clocks
and phase-locked loops (PLLs). Power is calculated automatically and subtotals
are given for each section. The calculator displays the estimated power usage in
the Total section.
Estimating Power While Creating the FPGA Design
When the FPGA design is partially complete, you can use the PowerPlay Early Power
Estimator file (<revision name>_early_pwr.csv) generated by the Quartus II software
to supply information to the PowerPlay Early Power Estimator. After importing the
power estimation file information into the PowerPlay Early Power Estimator, you can
edit the PowerPlay Early Power Estimator to reflect the device resource estimates for
the final design.
f
For more information about generating the power estimation file in the Quartus II
software, refer to the
chapter in volume 3 of the Quartus II
Handbook.
Table 2–1. Power Estimation Before Designing FPGA
Advantages
Disadvantages
■
Power estimation can be done
before the FPGA design is complete.
■
Accuracy depends on your input and estimate of the
device resources— this information can change during
or after the completion of your design, therefore
affecting the accuracy of your power estimation
results.
■
Process is time consuming.