Power saving techniques, Chapter 3. power saving techniques – Altera PowerPlay Early Power Estimator for Altera CPLDs User Manual
Page 27
December 2010
Altera Corporation
PowerPlay Early Power Estimator for Altera CPLDs User Guide
3. Power Saving Techniques
This chapter describes ways to reduce power cosumption.
The following guidelines reduce power consumption for an application:
■
Slow the operation in portions of the circuit. I
CC
is proportional to the frequency of
the operation. Slowing parts of a circuit lowers the I
CC
; therefore, reduces the
power. MAX II and MAX V devices provide global or array clock source for all
registers. Signals that do not require high-speed operation can use a slower array
clock that reduces the system power consumption.
■
Reduce the number of outputs. Standby and dynamic current are required to
support all the I/O pins on the device. Reducing the number of I/O pins can
reduce current necessary for the device thus reduces the power.
■
Reduce the loading and external capacitance on the outputs. Excessive loading
and capacitance of the PCB traces and other ICs on the output pins significantly
increases power. Keeping the excess load and external capacitance to a minimum
on the output pins whenever possible significantly reduces the current necessary
for the device.
■
Reduce the amount of circuitry in the device. Power depends on the amount of
internal logic that switches at any given time. Reducing the amount of logic in a
device reduces the current in the device and thus reduces the power.
■
Modify the design to reduce power. Identify areas in the design that you can revise
to reduce the power requirements. Common solutions include reducing the
number of switching nodes and required logic and removing any redundant or
unnecessary signals.
■
Modify the I/O Locations. Grouping the I/O pins from common logic blocks
allows the Quartus II software to place the associated logic closer together. The
more compact a logic block and I/O, the lower its dynamic power (this is
especially true of low utilization designs with the I/O spread around the device).
■
Increase the performance requirements in the constraint file. Improving the
performance that is beyond the need for operation reduces the power dissipation.
The Quartus II software optimizes the design and places logic closer together, uses
shorter routing and fewer logic levels, and lowers dynamic power and improves
performance.
f
MAX II and MAX V devices offer a power-down capability that conserves battery life
for portable applications. For more information about the power-down capability in
MAX II devices and an application design example, refer to
.