Altera PowerPlay Early Power Estimator for Altera CPLDs - Manual (Page 18)

2–8 Chapter 2: PowerPlay Early Power Estimator Worksheets
Power Estimation Using the PowerPlay Early Power Estimator
PowerPlay Early Power Estimator for Altera CPLDs User Guide December 2010 Altera Corporation
Figure 2–6 shows the T-Flipflop.
Figure 2–7 shows an example of a 4-bit counter.
Routing
This shows the power of dissipation due to the estimated routing.
Routing power depends on placement-and-routing information, which is a function of your
design complexity. The values shown represent the routing power based on experimentation of
more than 100 designs.
For detailed analysis based on your design’s routing, use the Quartus II PowerPlay Analyzer.
Block
This shows the power dissipation due to the internal toggling of the LEs.
Logic block power is a combination of the function implemented and the relative toggle rates of
the various inputs. The PowerPlay EPE spreadsheet uses an estimate based on an observed
behavior across more than 100 designs.
For accurate analysis based on your design’s exact synthesis, use the Quartus II PowerPlay
Analyzer.
Total
This shows the total power dissipation. The total power dissipation is the sum of the routing
and block power.
User Comments Enter any comments. This is an optional value.
Table 2–7. Logic Section Information (Part 2 of 2)
Column Heading Description
Figure 2–6. T-FlipFlop
Figure 2–7. 4-Bit Counter