Altera I/O Buffer (ALTIOBUF) IP Core - Manual

I/O Buffer (ALTIOBUF) IP Core User Guide
2014.12.15
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The ALTIOBUF megafunction IP core implements either an I/O input buffer (ALTIOBUF_in), I/O
output buffer (ALTIOBUF_out), or I/O bidirectional buffer (ALTIOBUF_bidir). You can configure the IP
core through the IP Catalog and parameter editor in the Quartus ® II software.
This user guide assumes that you are familiar with IP cores and how to configure them.
Related Information
Introduction to Altera IP Cores
Provides general information about Altera IP cores
ALTIOBUF Features
The ALTIOBUF IP core provides the following features:
• Capable of bus-hold circuitry
• Can enable differential mode
• Can specify open-drain output
• Can specify output enable port (
oe
)
• Can enable dynamic termination control ports for I/O bidirectional buffers
• Can enable series and parallel termination control ports for I/O output buffers and I/O bidirectional
buffers
• Can enable dynamic delay chains for I/O buffers
I/O Buffer and Dynamic Delay Integration
Altera recommends that you use the ALTIOBUF IP core to utilize the I/O buffers for any purpose that
includes LVDS interfaces (using the ALTLVDS IP core), DDR interfaces (using the ALTDDIO_IN,
ALTDDIO_OUT, ALTDDIO_BIDIR, ALTDQ, ALTDQS, and ALTDQ_DQS IP cores) and dynamic on-
chip termination (OCT) control (using the ALTOCT IP core).
ALTIOBUF Common Application
The I/O buffers have standard capabilities such as bus-hold circuitry, differential mode, open-drain
output, and output enable port.
One of the key applications for this IP core is to have more direct termination control of the buffers. By
enabling series and parallel termination control ports for the I/O output buffers and I/O bidirectional
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