Altera Dynamic Calibrated On-Chip Termination - Manual (Page 8)

February 2012 Altera Corporation Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction
User Guide
3. Functional Description
This chapter describes the functional description and the design examples of the
ALTOCT megafunction. This section also includes the ports descriptions of the
ALTOCT megafunction. You can use the ports to customize the ALTOCT
megafunction according to your application.
OCT Architecture
The OCT calibration architecture provides dynamic series and parallel on-chip
termination to improve I/O impedance matching and termination capabilities. OCT
improves signal quality over external termination through reduction of parasitic,
board space, and external component costs. The OCT architecture support RS with
and without calibration, RT with calibration, dynamic series and parallel termination
for single-ended I/O standards, and on-chip differential termination (RD) for
differential LVDS I/O standards. OCT is supported in all I/O banks by selecting one
of the OCT I/O standards.
Figure 3–1 shows the OCT calibration architecture in Stratix III devices. The SDATA ,
OCTUSRCLK , and ENASER signals are used to serially transfer calibrated codes from each
OCT calibration block to any I/O. To serially shift the 14-bit OCT RS calibration code
and the 14-bit OCT RT calibration code into the registers located in the I/O buffer, 28
clock cycles using
OCTUSRCLK are required. When calibration is complete, the 28-bit
OCT calibration code (14-bit OCT RS code and 14-bit OCT RT) must be serially shifted
out from each OCT calibration block to the corresponding I/O buffer.