About this megafunction, Features, Device support – Altera Dynamic Calibrated On-Chip Termination User Manual
Page 4: Chapter 1. about this megafunction, Features –1 device support –1

February 2012
Altera Corporation
Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction
User Guide
1. About this Megafunction
The Dynamic Calibrated On-Chip Termination (ALTOCT) megafunction is used in
double-data rate (DDR) external memory interfaces. This megafunction is closely
associated with the External DDR Memory PHY Interface (ALTMEMPHY)
megafunction. On-chip termination (OCT) improves signal quality over external
termination through reduced parasitic, board space, and external component costs.
Features
The ALTOCT megafunction provides the following features:
■
Support for up to 10 OCT blocks
■
Support for calibrated on-chip series termination (RS) and calibrated on-chip
parallel termination (RT) on all I/O pins
■
Calibrated termination values of 25 and 50 ohm
Device Support
TheALTOCT megafunction supports the following Altera
®
devices:
■
Arria
®
II GX
■
Arria II GZ
■
Arria V
■
Cyclone
®
V
■
HardCopy
®
III
■
HardCopy IV
■
Stratix
®
III
■
Stratix IV
■
Stratix V
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)