Altera Cyclone II FPGA Starter User Manual
Page 38

4–16
Altera Corporation
Cyclone II FPGA Starter Development Kit User Guide
October 2006
VGA Display
6.
Download the Raw_Data_Gray.dat file into the SRAM as described
in
“Displaying Another Image from a Downloaded Bitmap File” on
.
The ImgConv tool also generates a Raw_Data_BW.dat file (and its
corresponding TXT format) for the black and white version of the image.
The BW Threshold in
defines the threshold for judging black or
white level. Raw_Data_BW.txt fills in the MIF/Intel Hex format for M4K
SRAM.
Table 4–1. BW Threshold
Image Source
R/G/B Band Filter
B&W Threshold
Filter
Output Result
(640x480)
Color Picture
R/G/B
N/A
Raw_Data_Gray
Color Picture
R/G/B (optional)
BW Threshold
Raw_Data_BW +
Raw_Data_BW.txt
Grayscale Picture N/A
N/A
Raw_Data_Gray
Grayscale Picture N/A
BW Threshold
Raw_Data_BW +
Raw_Data_BW.txt
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)