Altera DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Manual
Page 7
Chapter 15: Introduction to ALTMEMPHY IP
15–7
Resource Utilization
November 2012
Altera Corporation
External Memory Interface Handbook
Volume 3: Reference Material
shows resource utilization data for the DDR2 high-performance controller
and controller plus PHY, for half-rate and full-rate configurations for Arria II GX
devices.
Controller+PHY
DDR3
(Half rate)
8
3,389
2,760
12
4
0
4,672
16
3,457
2,856
12
7
0
9,280
64
3,793
3,696
20
24
0
36,672
72
3,878
3,818
12
26
0
41,536
Table 15–8. DDR2 Resource Utilization in Arria II GX Devices
Protocol
Memory
Width
(Bits)
Combinational
ALUTS
Logic
Registers
Mem
ALUTs
M9K
Blocks
M144K
Blocks
Memory
(Bits)
Controller
DDR2
(Half rate)
8
1,971
1,547
10
2
0
4,352
16
1,973
1,547
10
4
0
8,704
64
2,028
1,563
18
15
0
34,560
72
2,044
1,547
10
17
0
39,168
DDR2
(Full rate)
8
2,007
1,565
10
2
0
2,176
16
2,013
1,565
10
2
0
4,352
64
2,022
1,565
10
8
0
17,408
72
2,025
1,565
10
9
0
19,584
Controller+PHY
DDR2
(Half rate)
8
3,481
2,722
12
4
0
4,672
16
3,545
2,862
12
7
0
9,280
64
3,891
3,704
20
24
0
36,672
72
3,984
3,827
12
26
0
41,536
DDR2
(Full rate)
8
3,337
2,568
29
2
0
2,176
16
3,356
2,558
11
4
0
4,928
64
3,423
2,836
31
12
0
19,200
72
3,445
2,827
11
14
0
21,952
Table 15–7. Resource Utilization in Arria II GX Devices (Part 2 of 2)
Protocol
Memory
Width
(Bits)
Combinational
ALUTS
Logic
Registers
Mem
ALUTs
M9K
Blocks
M144K
Blocks
Memor
y (Bits)