Altera DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP - Manual (Page 6)

15–6 Chapter 15: Introduction to ALTMEMPHY IP
Unsupported Features
External Memory Interface Handbook November 2012 Altera Corporation
Volume 3: Reference Material
Unsupported Features
Table 15–6 summarizes unsupported features for Altera’s ALTMEMPHY-based
external memory interfaces.
MegaCore Verification
Altera performs extensive random, directed tests with functional test coverage using
industry-standard Denali models to ensure the functionality of the DDR, DDR2, and
DDR3 SDRAM Controllers with ALTMEMPHY IP.
Resource Utilization
This section provides typical resource utilization information for the external memory
controllers with ALTMEMPHY for supported device families. This information is
provided as a guideline only; for precise resource utilization data, you should
generate your IP core and refer to the reports generated by the Quartus II software.
Table 15–7 shows resource utilization data for the ALTMEMPHY megafunction, and
the DDR3 high-performance controller II for Arria II GX devices.
Table 15–6. Unsupported Features
Memory Protocol Unsuppoted Feature
DDR and DDR2 SDRAM
Timing simulation
Burst length of 2
Partial burst and unaligned burst in ECC
and non-ECC mode when DM pins are
disabled
DDR3 SDRAM
Timing simulation
Partial burst and unaligned burst in ECC
and non-ECC mode when DM pins are
disabled
Stratix III and Stratix IV
DIMM support
Full-rate interfaces
Table 15–7. Resource Utilization in Arria II GX Devices (Part 1 of 2)
Protocol
Memory
Width
(Bits)
Combinational
ALUTS
Logic
Registers
Mem
ALUTs
M9K
Blocks
M144K
Blocks Memor
y (Bits)
Controller
DDR3
(Half rate)
8 1,883 1,505 10 2 0 4,352
16 1,893 1,505 10 4 0 8,704
64 1,946 1,521 18 15 0 34,560
72 1,950 1,505 10 17 0 39,168