Input path waveform – Altera GPIO User Manual
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Note: The Altera GPIO megafunction does not support dynamic calibration of the input path. For
applications requiring dynamic calibration of the input path, refer to the
.
After data goes to the output of the delay element, programmable bypass multiplexers select the features
and paths to use. Each input path contains two stages of DDIOs, which are full-rate and half-rate.
Note: When you set the Register mode option to Simple register, the full-rate DDIO works as a simple
register.
Note: When you set the Register mode option to Simple register, the Fitter chooses whether to pack the
register in the I/O or implement the register in the core, depending on the area and timing trade-
offs.
Use the input path in four modes:
• Bypass—data goes from the delay element to the core, bypassing all DDIOs.
• Packed Register—the full-rate DDIO operates as a register, bypassing half-rate DDIOs.
• Double data rate Input/Output (DDIO) mode with full-rate conversion—The full-rate DDIO operates
as a regular DDIO, bypassing half-rate DDIOs.
• DDIO mode with half-rate conversion—The full-rate DDIO operates as a regular DDIO. Half-rate
DDIOs converts data for full-rate to half-rate.
All DDIOs share the same asynchronous clear and preset signals when used. Half-rate and full-rate
DDIOs connect to separate clocks. When you use half-rate and full-rate DDIOs, the full-rate clock must
run at twice the half-rate frequency. Use different phase relationships to meet timing requirements.
Input Path Waveform
The following figure shows the waveforms for an input path in DDIO mode with half-rate conversion.
This configuration uses all the blocks and refers to the same labels shown in
Note: The actual timing relationship between different signals may vary depending on the specific design,
delays, and phases that you choose for the full-rate and half-rate clocks.
ug-altera_gpio
2014.08.18
Input Path Waveform
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Altera GPIO IP Core User Guide
Altera Corporation