Altera GPIO - Manual (Page 21)

mode. The Fitter will attempt to configure the IOPLL for a better setup and hold slack of the input I/O
timing analysis.
For the output and output enable registers of the Altera GPIO IP core, you can use the output delay chain
and output enable delay chain to add delay to the output data and the output clock. If setup time violation
is observed, you can increase the delay chain setting of the output clock. If hold time violation is observed,
you can increase the delay chain setting of output data.
Design Example
The Altera GPIO IP core is able to generate a design example that matches the same configuration chosen
for the IP. The design example is a simple design that does not target any specific application; however
you can use the design example as a reference on how to instantiate the IP core and what behavior to
expect in a simulation.
Note: The .qsys files are for internal use during example design generation only. You cannot edit the files.
Generating Design Example
During generation, the Generation dialog box displays the option to generate a design example. Turn on
the Generate Example Design option.
The software generates the _example_design directory along with the IP, where is
the name of your IP.
The _example_design directory contains two TCL scripts:
•
- make_qii_design.tcl
•
- make_sim_design.tcl
Generating Quartus Design Example
The
make_qii_design.tcl
generates a synthesizable design example along with a Quartus project, ready
for compilation.
To generate synthesizable design example, run the following script at the end of IP generation:
quartus_sh -t make_qii_design.tcl
To specify an exact device to use, run the following script:
quartus_sh -t make_qii_design.tcl [device_name]
This script generates a qii directory containing a project called ed_synth.qpf. You can open and compile
this project with the Quartus II software.
Generating Simulation Design Example
The
make_sim_design.tcl
generates a simulation design example along with tool-specific scripts to
compile and elaborate the necessary files.
To generate a simulation design example, run the following script at the end of IP generation:
quartus_sh -t make_sim_design.tcl
ug-altera_gpio
2014.08.18
Design Example 21
Altera GPIO IP Core User Guide Altera Corporation
Send Feedback