Power management controller reference design, Power management controller reference design -1 – Altera MAX 10 Power User Manual
Page 14
Power Management Controller Reference
Design
3
2015.02.09
UG-M10PWR
This reference design utilizes the low-power feature supported in MAX 10 devices. The following figure
shows the related block diagrams in the power management controller reference design.
Figure 3-1: Power Management Controller Block Diagram
PMC
(altera_pmc)
Internal Oscillator
(altera_int_osc)
sleep
rst_n
Clock Control Block
(clk_control_altclkctrl)
clk_osc
clk
I/O Buffer
(altera_gpio_lite)
User
Logic
sleep_status
gpio_pad_output[3:0]
cnt_enter_sleep[7:0]
cnt_value[7:0]
cnt_exit_sleep[7:0]
clk_gated
ioe
clk_ena
The following table lists the input and output ports of the reference design.
Table 3-1: Input and Output Ports of the Power Management Controller Reference Design
Port Name
Input/Output
Description
sleep
Input
Sleep control.
rst_n
Input
Active low reset signal.
clk
Input
Clock signal.
sleep_status
Output
Sleep status of the system. This signal
is asserted high when the system is
entering the sleep mode condition.
This signal is de-asserted when the
system exits the sleep mode condition
completely.
gpio_pad_output[3:0]
Output
General-purpose I/O (GPIO) output
ports.
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