Spectrum Controls 140 EHC 204 00sc - Manual (Page 42)

Counter / Flow Meter Input Module
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Counter Preset Flag: Bit 15
When the Counter Preset value is reached this flag bit is set. The bit is reset when the counter
in incremented up or down from the Preset value.
Gate Enable Echo: Bit 14
This bit echos the state of the gate enable line. The gate enable line is an external logic line
used to time counter events.
Counter Invert Echo: Bit 13
This bit echos the state of the counter direction. The invert flag indicates if the invert bit has
been set. It is not an absolute indication of direction but instead an indication that the starting direc-
tion has been changed. For example: If the counter begins in a downward direction and the bit it set,
Counter Input State: Bit 12
This bit shows the current value of the output state. The state of the output will be sampled at
the end of the current update cycle. For rapidly changing counter inputs the state of this bit could be
either high or low depending on the exact time of measurement. This purpose for this bit is to
provide slow counter feedback and single count diagnosis. This bit can also be used as a general-
purpose digital input line back to the PLC.it will invert direction to an upward mode.
Quadrature Direction State: Bit 11
This bit shows the current direction of the quadrature encoder. The state of the encoder will be
sampled at the end of the current update cycle. For rapidly changing counter inputs the state of this
bit could be either high or low depending on the exact time of measurement. This purpose for this
indicator is to provide quadrature detection feedback to aid in system diagnosis.
Count Size Selection Echo: Bit 10
This bit echo’s the state of the maximum counter value selected in the configuration register.
When reset to zero the channel counter will count up to 65K (1 word of data). When the counter at
65K the maximum count value is reached, the Maximum Count flag is set, and rollover will occur at
this point. Channel update time should be faster if the counter values are set to 65K. The level of
speed improvement will need to be determined. When the count size is extended to 16M, the
Counters Maximum flag is extended to 16M. The counter Preset and Limit values are also extended
to 16M. This means that the resolution of the Preset and Limit values are set in blocks of 256 counts
(8bits). This allows the preset and limit values to cover the whole 16M bit range.
Counter Max Flag: Bit 9:
This flag indicates that the counters accumulator has reached its maximum count value. When
the counter value is greater then or equal to the Max value the Counter Limit flag bit will be set. The
Max flag will stay set until the Reset Flags bit is toggled in the channels’ configuration register. The
Max flag is set at 65,536 and 16,777,216 depending on the data output mode.
Note that the internal counter H/W will set is Max flag when the counter is at –1 for both 65K
and 16M modes.