Spectrum Controls 140 EHC 204 00sc - Manual (Page 36)

Counter / Flow Meter Input Module
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Preset, Bit 15
Set bit 15 to 1 to load the counter preset value into the counter. This value is used to set the
counter to an initial starting value. Set bit 15 for at least one I/O scan, and hold it on until counter
data is verified to be equal to the preset value. The counter holds the preset value until the bit 15 is
turned off (set to 0). At this time normal counter functions resume.
NOTE A counter preset function begins when bit 15 is set to 0.
Reset Counter, Bit 14
This bit resets the counter. When this bit is set the count value will go to zero and all flags will
be reset.
Gate Enable, Bit 13
Set bit 13 to 1 to enable the 5-24VDC pulse-to-enable circuit used during meter proving. This
bit should be set to 0 at all other times.
Count Direction, Bit 12
Bit 12 determines the count direction for a counter. Normally you will set this bit to 0 to count
up, and to 1 to count down. For a quadrature encoder, however, a setting of 0 uses the normal
quadrature decode direction. A setting of 1 inverts the direction.
Reset Flags, Bit 11
Bit 11 is used to reset the internal flags that indicate the maximum, limit, and zero conditions
for the counter and the input rate. The flags are defined in the following table.
Table 3-6 Reset Flags
Flag
Maximum
For the Counter
Indicates when the count passes the counter maximum. The maximum depends on the count size, described in
“Count Size, Bit 9” on page S Section header]1. The maximum is set at 65,536 for standard mode or
16,777,216 for extended mode. The status of the flag is reflected in the counter maximum bit in the 3X state
register register for the channel. See “ Counter Limit State, Bit 10”.
For the Input Rate
Indicates when the input rate exceeds the maximum range for the rate mode, described in “ Rate Mode, Bit 12”
on page S Section header]1. The status of the flag is reflected in the rate maximum bit in the 3X state register
for the channel. See “ Rate Maximum State, Bit 7”.
Limit
For the Counter
Indicates when the count passes the counter limit. The limit depends on the count size, described in “ Count
Size, Bit 9” on page S Section header]1 . The status of the flag is reflected in the counter limit bit in the 3X
state register register for the channel. See “ Counter Limit State, Bit 10”.
For the Input Rate
Indicates when the input rate exceeds the non-zero limit set in the rate limit/R data register, and that the input
rate is above it limit (see “ Contents of Registers 4X+4 and 4X+8” on page S Section header]1 ). The status
of the flag is reflected in the rate limit bit in the 3X state register register for the channel. See “ Rate Limit