Spectrum Controls 140 MPM 204 00sc - Manual (Page 41)

Meter Proving Module
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Pulse Fidelity: Bit 15 Pulse Fidelity: Bit 15 Pulse Fidelity: Bit 15 Pulse Fidelity: Bit 15 Pulse Fidelity: Bit 15
This bit activates the pulse fidelity feature.
Meter Meter Meter Meter Meter Pr Pr Pr Pr Proving Finished/Not Finished: Bit 14 oving Finished/Not Finished: Bit 14 oving Finished/Not Finished: Bit 14 oving Finished/Not Finished: Bit 14 oving Finished/Not Finished: Bit 14
This bit indicates whether the meter-proving run has finished or not. When the Meter proving
bit (Gate enable on the control register) gets set, the meter proving process will begin. This consists
of counting the number of pulses from the first ball detector pulse till the second ball detector pulse.
When the second ball detector pulse is detected, the proving run is complete and this bit will be set.
Meter proving data is now ready to be read from the 3X registers.
Pulse Fidelity Count Err Pulse Fidelity Count Err Pulse Fidelity Count Err Pulse Fidelity Count Err Pulse Fidelity Count Error: Bit 13 or: Bit 13 or: Bit 13 or: Bit 13 or: Bit 13
When pulse fidelity checking is enabled, this bit will annunciate whether a count error has
occurred. The error detector continuously samples the input signal. A count difference between the
two channels of 3 or more will result in a count error. Software reads of channel pairs are synchro-
nized so that ladder logic will read both values taken simultaneously. Thus ladder logic can ignore
this bit and set its own error limit. This fault is not latched. It persists only as long as the actual
fault.
Pulse Fidelity Fr Pulse Fidelity Fr Pulse Fidelity Fr Pulse Fidelity Fr Pulse Fidelity Frequency Err equency Err equency Err equency Err equency Error: Bit 12 or: Bit 12 or: Bit 12 or: Bit 12 or: Bit 12
When pulse fidelity checking is enabled, this bit will annunciate whether a frequency error has
occurred. The error detector continuously samples the input signal at TBD rate. Three consecutive
erroroneous readings (error threshold 10%) will result in a frequency error.
Pulse Fidelity Phase Err Pulse Fidelity Phase Err Pulse Fidelity Phase Err Pulse Fidelity Phase Err Pulse Fidelity Phase Error: Bit 1 or: Bit 1 or: Bit 1 or: Bit 1 or: Bit 11 1 1 1 1
When pulse fidelity checking is enabled, this bit will annunciate whether a phase error has
occurred. The error detector continuously samples the input signal at TBD rate. Three consecutive
erroroneous readings (error threshold+/-30 degrees) will result in a phase error.
Pulse Fidelity Sequency Err Pulse Fidelity Sequency Err Pulse Fidelity Sequency Err Pulse Fidelity Sequency Err Pulse Fidelity Sequency Error: Bit 10 or: Bit 10 or: Bit 10 or: Bit 10 or: Bit 10
When pulse fidelity checking is enabled, this bit will annunciate whether a sequence error has
occurred. The error detector continuously samples the input signal at TBD rate. Three sequence
errors detected in one minute will result in a sequence error. The sequence error should be latched
in Software. It will remain latched until the “clear flags” command clears it.
Counter Input State: Bit 9 Counter Input State: Bit 9 Counter Input State: Bit 9 Counter Input State: Bit 9 Counter Input State: Bit 9:
This bit shows the current value of the input state. The state of the input is sampled at the end
of the current update cycle. For rapidly changing counter inputs the state of this bit could be either
high or low depending on the exact time of measurement. This purpose for this bit is to provide
slow counter feedback and single count diagnosis. This bit can also be used as a general-purpose
digital input line back to the PLC.and 16M modes.