Spectrum Controls 140 MPM 204 00sc User Manual
Page 40
Quantum Series 140 MPM 204 00sc
42
Bit Settings for 3X Registers
Bit Settings for 3X Registers
Bit Settings for 3X Registers
Bit Settings for 3X Registers
Bit Settings for 3X Registers
The 3X registers (3X+1 through 3X+8) contain data and status information for channels 1
through 8. You can only set 3X register bits using ladder logic. This section describes the layout for
the status registers (3X+1 through 3X+8) and defines the bits. Ladder logic examples are provided
in chapter 4, “Programming.”
T
T
T
T
Table 3-6 3X+9 to 3x+10 Register
able 3-6 3X+9 to 3x+10 Register
able 3-6 3X+9 to 3x+10 Register
able 3-6 3X+9 to 3x+10 Register
able 3-6 3X+9 to 3x+10 Register Bit Settings (Channel Status
Bit Settings (Channel Status
Bit Settings (Channel Status
Bit Settings (Channel Status
Bit Settings (Channel Status W
W
W
W
Words 3x+9 - Bank 0, 3X+10 - Bank 1)
ords 3x+9 - Bank 0, 3X+10 - Bank 1)
ords 3x+9 - Bank 0, 3X+10 - Bank 1)
ords 3x+9 - Bank 0, 3X+10 - Bank 1)
ords 3x+9 - Bank 0, 3X+10 - Bank 1)
Function
Function
Function
Function
Function
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
5
5
5
5
5
6
6
6
6
6
7
7
7
7
7
8
8
8
8
8
9
9
9
9
9
10
10
10
10
10
1
1
1
1
11
1
1
1
1 12
12
12
12
12 13
13
13
13
13 14
14
14
14
14
15
15
15
15
15 16
16
16
16
16
Enable
Start
0
Stop
1
Pulse
Fidelity
Disable
0
Enable
1
Meter
Proving
Not
Finished
0
Finished
1
Pulse
Fidelity
No
Error
0
Count
Error
Error
1
Pulse
Fidelity
No
Error
0
Frequency
Error
Error
1
Pulse
Fidelity
No
Error
0
Phase
Error
Error
1
Pulse
Fidelity
No
Error
0
Sequence
Error
Error
1
Counter Input
Off
0
State
On
1
Preset to other
No preset
0
Channels
Value
Preset
1
Unused
X
Over
Rate
Flag
Reset
0
Set
1
Rate Limit Flag
Reset
0
Set
1
Rate Zero Flag
Reset
1
Set
0
K&M
Factor
Set
Zero
1
Flag
Set
0
R
Factor
Set
Zero
1
Flag
Set
0
Configuration
OK
0
Error Flag
Error
1
Enable Start/Stop Echo: Bit 16
Enable Start/Stop Echo: Bit 16
Enable Start/Stop Echo: Bit 16
Enable Start/Stop Echo: Bit 16
Enable Start/Stop Echo: Bit 16
This bit echoes the setting of the Counter Enable bit set in the channels control register. The
counter enable bit allows the counter to continue to count up or down from its present value. Start-
ing or enabling the counter with this bit will not override the external counter input. Both the exter-
nal input enable and the counter start bit must be enabled for the counter to continue counting. If
either the counter stop bit or the external input enable line are disabled the counter will hold its last
value and stop counting.