Spectrum Controls 140 MPM 204 00sc User Manual

Page 36

Quantum Series 140 MPM 204 00sc

Pulse Fidelity

Pulse Fidelity, Bit 15

, Bit 15

When this bit is enabled, the module will perform pulse fidelity monitoring of an input channel

pair. The bit needs to be set on both channels being monitored. For example both channels 1 and 2
must have this bit set to do pulse fidelity monitoring on channels 1 and 2. Both channels must have
the same configuration settings, such as input range, for pulse fidelity to be performed. If they do
not, then a configuration error will be set.

This module performs level B pulse fidelity to level B per API specification. Level B consists

of continuous comparison of pulse trains for number, frequency, phase, and sequence.

Reset Counter

Reset Counter, Bit 14

, Bit 14

This bit resets the counter. When this bit is set the count value will go to zero and all flags will

be reset. This bit also clears any pulse fidelity errors.

Meter

Meter Pr

Proving

oving

oving Arm

Arm

Arm, Bit 13

, Bit 13

This bit (when set to 1) enables the meter-proving circuit. This function is used during meter

proving, allowing pulse interpolation to be activated when the prover cycle is running. This bit
should be set to 0 at all other times.

Meter

Meter Pr

Proving Mode, Bit 12

oving Mode, Bit 12

Bit 12 determines the meter proving run is unidirectional or bi-directional. Normally this bit is

set to 0 for single direction prover runs. The bit should be set to 1 for a bi-directional prover run.

Reset Flags, Bit 1

Reset Flags, Bit 11

Bit 11 is used to reset the internal flags that indicate the maximum count condition for the

counter and the input rate. The flags are defined in the following table.

Table 3-6 Reset Flags

able 3-6 Reset Flags

Flag

Flag
Maximum

Maximum

For the Input Rate

For the Input Rate
Indicates when the input rate exceeds the maximum range for the rate mode, described in “ Rate Mode, Bit 8

Rate Mode, Bit 8

Rate Mode, Bit 8”

on page 41. The status of the flag is reflected in the rate maximum bit in the 3X state register for the channel.
See “ Rate Maximum State, Bit 7

Rate Maximum State, Bit 7

Rate Maximum State, Bit 7”.

Setting bit 11 to 0 latches the normal state of the flags until they are reset. This allows the

ladder logic program to monitor the state of the flags and reset them (to 1) as needed when parameter
settings change. Setting bit 11 to 1 reports the counter flags to the PLC for one scan cycle, and then
resets them automatically. If the maximum, limit, or zero condition still exists, the module sets the
flags back to 1 on the next update cycle.

NOTE:

NOTE: You can use bit 11 to reset the reset flags as a counter value passes through a maxi-

mum range value. However, the two values cannot be equal at the time the counter value is read
from the backplane. For example, if the counter limit is set to 10,000, the counter limit flag is set
when the count exceeds 10,000. The next count value transferred to the rack might be 10,050. The
status register will have the counter maximum range flag set for this transfer of counter data.

Not Used, Bit 10,9