ADLINK Express-IBR - Manual (Page 33)

Chapter 3 Hardware
Express-IBR Reference Manual 27
Power Management
The Express-IBR is ACPI 4.0a compliant. The board supports S0, S1, S3, S4, and S5 sleep states.
Video Interfaces
VGA
The Express-IBR graphics are driven by an Intel internal graphics interface which provides the interface for
an analog display. A 340-MHz integrated, 32-bit RAM-based, Digital-to-Analog Converter (RAMDAC)
converts up to 2048x1536 digital pixels at a maximum refresh rate of 75-Hz. Three 8-bit DACs provide
R, G, B signals to the monitor.
LVDS
The Intel BD82QM77 PCH provides direct LVDS output. The output is independent of other panel
interfaces. The LVDS interface will support 1 or 2 channels and can support four data pairs and one clock
pair of LVDS (18 or 24-bit) in each channel.
Audio Interface
The High Definition (HD) Audio controller resides in the PCH and communicates with external codec(s)
(such as audio and modem codecs) over the Intel HD Audio serial link. The PCH implements a single Serial
Data Output signal (AC/HDA_SDOUT) that is connected to all external codecs. Four Serial Digital Input
signals (AC/HDA_SDIN) support up to four codecs.
Ethernet Interface
The Express-IBR supports one Gigabit Ethernet interface, which can be enabled in BIOS Setup. The
Ethernet interface is implemented from the 82579LM Ethernet transceiver and occupies PCI Express port 8.
The Ethernet function supports multi-speed operation at 10/100/1000 Mbps and operates in full-duplex at all
supported speeds or half duplex at 10/100 Mbps while adhering to the IEEE 802.3x flow control
specification.
I ² C
™
Bus
The I²C bus is implemented through the use of the Atmel ATmega168 board controller. The board controller
provides a Fast Mode (400kHz max.) multi-master I²C bus that has maximum I²C bandwidth. Use the
ADLINK Intelligent Device Interface (AIDI) Library for access to the I²C bus. AIDI driver information is
available on the Express-IBR Product page at: http://www.adlinktech.com . An AIDI demo program and the
AIDI User’s Manual describing how to use the I²C bus also reside in the Utilities tab of the Express-IBR
Product page.
PCI Express
™
The Express-IBR offers six (6) PCI Express x1 lanes (lanes 1-6) through the COM Express A-B connector
and one PCI Express x1 lane (lane 7) through the C-D connector. These lanes can be configured to support
PCI Express edge cards or ExpressCards. Each x1 lane supports up to 5 GT/s bandwidth in each direction.
Lanes 1-4 can be configured through the BIOS setup utility as four x1s or one x4 lane widths. Lanes 5-7
each can be independently enabled or disabled through the BIOS setup utility. The eighth x1 lane (lane 8) is
utilized by the on-board Gigabit Ethernet transceiver and is not available as a PCIe lane. The PCI Express
interface is based on the PCI Express Specification 2.0. The C-D connector also provides one PCIe x16
interface for a PCIe graphics (PEG) card or other PCIe expansion cards and can be configured using the on-
board configuration switch (SW1).