ADLINK Express-IBR - Manual (Page 28)

Chapter 3 Hardware
22 Reference Manual Express-IBR
CPU
The Express-IBR offers five versions of the Intel  Core™ i CPU—the i3-3217UE, i7-3517UE, i7-3612QE,
i7-3615QE, and i7-3555LE—operating at 1.8GHz, 1.7GHz, 2.1GHz, 2.3GHz, and 2.5GHz, respectively.
The CPU integrates a high-performance, 64-bit, x86 multi Processor Core with Memory Controller and 3D
Graphics Engine. This single chip is based on 32-nm process technology and provides an Intel Flexible
Display Interface and a Direct Media Interface for high-speed connectivity to the PCH. The CPU also
supports Intel Hyper-Threading Technology (4 cores, 8 threads) and up to 16GB of DDR3 memory at
1333/1600MHz for high overall performance.
Graphics
The CPU provides a refresh of the seventh generation graphics core, which features a substantial gain in
performance and a decrease in power consumption. The next generation Intel Clear Video HD Technology
includes a collection of video playback and enhancement features that improve the end user’s viewing
experience including Encode/Transcode HD content, HD content playback, and superior image quality.
Other graphics features of the CPU include support for DirectX 11.0, OpenGL 3.1, DirectX Video
Acceleration (DXAV), Advanced Scheduler 2.0, 1.0, and XPDM.
Memory
The Express-IBR features dual-stacked SODIMM sockets for up to 16GB of DDR3 memory. The CPU
provides an Integrated Memory Controller (IMC) with DDR3 protocols and two independent, 64-bit wide
channels each supporting one un-buffered ECC SODIMM and employing up to two device ranks per
channel. Single-channel mode is available when either Channel A or Channel B is populated, but not both.
In dual-channel mode, both Channels must be populated and the SODIMM in Channel A must be greater or
equal in size to the SODIMM in Channel B.
NOTE ADLINK Technology, Inc. only supports the features/options tested and listed in
this manual. The main chips used in the Express-IBR may provide more features
or options than are listed for the Express-IBR, but some of these features/options
are not supported on the module and will not function as specified in the chip
documentation.