ADLINK PCI-9846 - Manual (Page 55)

Operation Theory 45
Figure 3-18: SSI Architecture
For PCI-9816/26/46, a dedicate connector is served as system
synchronization interface. Refer to Figure 3-19 for the connector
position. All the SSI signals are routed to the 20-pin connector
from FPGA. With this interface, PCI-9816/26/46 is capable of
achieving multiple module synchronization. Users can use ACL-
SSI-2/ACL-SSI-3/ACL-SSI-4 cables to synchronize 2, 3, or 4 mod-
ules. Please refer to Figure 3-20 for the installation of an ACL-SSI
cable.
Note: When powering-up or reseting, the synchronization sig-
nals are reset to use internal generated timing signals.
Trigger
Decision
SSI_TRG1
SSI_TRG2
SSI_START_OP
SSI_TIMEBASE
P
X
I I
n
ter
fa
ce or
S
S
I
PXI Trigger
Bus[0:7]
or
SSI
Timing Control