ADLINK PXI-2208 - Manual (Page 76)

64 Operation Theory
4.3 Digital I/O
The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card contains 24
lines of general-purpose digital I/O (GPIO) which is provided
through the 82C55A chip.
The 24-line GPIO are separated into three ports: Port A, Port B
and Port C. Port A and Port B can be programmed to be either
input or output ports. Port C can be separated into high bit (PC4-
PC7) and low bit (PC0-PC3), and both high bit and low bit ports
can be programmed for input or output. Upon system startup or
reset, all the GPIO pins are reset to high impedance inputs.
The DAQ/DAQe/PXI-2010 also provides two digital inputs per
channel (SDI from CN2), which are sampled simultaneously with
an analog signal input and is stored with the 12-bit AD data. Refer
to Figure 4.1 for the more details.
4.4 General Purpose Timer/Counter Operation
NOTE The DAQ-/DAQe-/PXI-2208 card does not support this
function.
Two independent 16-bit up/down timer/counter are designed
within FPGA for various applications. They have the following fea-
tures:
X
Count up/down controlled by hardware or software
X
Programmable counter clock source (internal or external
clock up to 10 MHz)
X
Programmable gate selection (hardware or software con-
trol)
X Programmable input and output signal polarities (high active
or low active)
X
Initial count can be loaded from software
X
Current count value can be read-back by software without
affecting circuit operation