ADLINK PXI-2208 - Manual (Page 46)

34 Operation Theory
Figure 4-1: Synchronous Digital Inputs Block Diagram
Figure 4-2: Synchronous Digital Inputs Timing
NOTE Since the analog signal is sampled when an A/D conver-
sion starts (falling edge of A/D_conversion signal), while
SDI<3..0> are sampled right after an A/D conversion
completes (rising edge of nADBUSY signal). Precisely
SDI<3..0> are sampled with 280ns lag to the analog sig-
nal.
ADC
AD<11..0>
16-bit
Register
SDI<3..0>
from CN2
From
Instrumentation
Amplifier
4
12
16
AD
Data
FIFO Ain
SDI<3..0>
CLK nADBUSY
nADCONV
AD_conversion
nADBUSY
AD_conversion
nADBUSY
16 bits data(including AD<11..0> and SDI<3..0>
latched into AD Data FIFO