2 status registers specified by ieee488.2, 2 status registers specified by ieee488.2 -4 – Anritsu MP1777A User Manual
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6.2
Status Registers Specified by IEEE488.2
IEEE488.2 specifies the two status registers shown below.
Section 6 Status Report
Table 6-2
Definitions of Status Registers Specified by IEEE488.2
Status Register
Definition
Status byte register
A register to set RQS and seven summary message bits.
Being used in combination with the service request enable register, this register sets
SQR ON when the logical OR of the two is not zero. RQS is system reserved in bit 6
and this bit reports to the external controller the presence of service request.
Standard event status register
Sets eight types of events the device will encounter as standard events.
The logical OR output bit is summarized and displayed in bit 5 of the status byte
register as the ESB (Event Status Bit) summary message.
Standard event status
enable register
0
1
Standard event
status register
—
0
Logica OR
Service request
enable register
0
1
OPC
NOT USED
QYE
DDE
EXE
CME
NOT USED
PON
Error/event queue
Status byte
register
0
NOT USED
NOT USED
OUE-----------
QUES---------
MAV ---------
ESB ----------
Output queue
►MSS6 RQS-
7 OPER
Logical OR
i
Service Request
Generation
QUEStionable
status register
OPERation
status register
6-4
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