Maxim Integrated 71M6534 Energy Meter IC Family Software - Manual (Page 105)

71M653X Software User’s Guide
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6 80515 MPU REFERENCE
An 80515 core is implemented on the TERIDIAN 71M653X chips. This section is intended for software engineers who
plan to use the 80515.
The MPU core is described in detail in the 6531, 6533, and 6534 data sheets, except for the instruction set, which is
presented in this chapter.
6.1 THE 80515 INSTRUCTION SET
All 80515 instructions are binary code compatible and perform the same functions as they do with the industry standard
8051. The following tables give a summary of the instruction set cycles of the 80515 MPU core.
Table 6-7 and Table 6-8 contain notes for mnemonics used in instruction set tables.
Table 6-9 through Table 6-17 show the instruction hexadecimal codes, the number of bytes, and the number of
machine cycles required for each instruction to execute.
Rn Working register R0-R7
direct 256 internal RAM locations, any Special Function Registers
@Ri Indirect internal or external RAM location addressed by register R0 or R1
#data 8-bit constant included in instruction
#data 16 16-bit constant included as bytes 2 and 3 of instruction
bit 256 software flags, any bit-addressable l/O pin, control or status bit
A Accumulator
Table 6-1: Notes on Data Addressing Modes
addr16 Destination address for LCALL and LJMP may be anywhere within the 64-kB of program memory
address space.
addr11 Destination address for ACALL and AJMP will be within the same 2-kB page of program memory
as the first byte of the following instruction.
rel SJMP and all conditional jumps include an 8-bit offset byte. Range is +127/-128 bytes relative to
the first byte of the following instruction
Table 6-2: Notes on Program Addressing Modes
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