Maxim Integrated 71M6534 Energy Meter IC Family Software - Manual (Page 100)

71M653X Software User’s Guide
enough time to write one byte before the next CE run starts. This would confine a transparent flash write scheme to a
maximum data rate of 2520 bytes per second. If the MPU disables interrupts at all, the write can miss the window and
fail. In this case, the write can detect a failure to write by examining and clearing the FWCOL0 bit. If the FWCOL1 bit
is set, the write was in progress when the CE pass should have started. In this case, the code must count the failed
CE code passes and prorate the metering data. Prorating the metering data is unacceptable to many users.
5.17.8 Watchdog Location
The watchdog reset bit moved to bit 7 of SFR 0xF8. The other bits of this register are read-only.
5.17.9 Software Watchdog Now Deprecated
The 651x series had a software watchdog that was part of the 8051 core, and which could be disabled by software.
The 653x series no longer supports the core’s watchdog. Instead, use the standard watchdog, which cannot be
disabled by software.
5.17.10 Real Time Clock Compensation
The real-time clock compensation is very different from the 651x series. Fixed rate adjustments are nonvolatile and
automatic, so that they continue when the MPU is not operating.
The 32 KHz crystal rate can be measured precisely in the factory by using a precision frequency counter to measure
the 1 second or 4 second output from the TMUX pin. During this measurement, the RTCA_ADJ register should be set
to the middle of its range, 0x40, and PREG and QREG should be set to the middle of their range.
After this, the capacitance driving the crystal can be adjusted by have the meter software write and preserve a value for
the real time clock analog adjustment, RTCA_ADJ XDATA 0x2011.
After RTCA_ADJ is set, the clock rate can be remeasured using the frequency counter with TMUX.
In operation the clock’s rate can be digitally adjusted for temperature or to follow the line frequency by adjusting the
PREG and QREG registers. These are actually a single register that adds or subtracts a count after a certain number
of counts.
Setting PREG and QREG to zero will cause the seconds register to count at ½ Hz, rather than 1 Hz.
5.17.11 Battery Modes
One of the most significant innovations for the 71M653x is the battery-power feature. This feature provides three
operational modes that apply when the supply voltage is removed and the chip is powered by the battery. The
operation modes and their transitions are shown in Figure 5-5, State Diagram of Operating Modes.
In the brownout mode, operation continues at 32kHz, and RAM and DIO pins remain powered. However, the clock
slows down and is so slow that the timers and serial port give dramatically different timings. Only the RTC, and its 1-
second interrupt run at an unchanged speed.
In addition to the flags given in Figure 5-5, State Diagram of Operating Modes, the following considerations apply to
state transitions:
• Mission to brownout mode: The MPU keeps running, but the clock slows down.
• Brownout to mission mode: The MPU keeps running, but the clock speeds up.
• LCD or sleep mode to brownout mode: The MPU will start code execution at address 0x000.
The sleep and LCD modes shut down all of the 71M653x’s internal and XDATA RAM, as well as the pin drivers for
DIOs, and most of the memory cells that store the hardware configuration.
The lack of nonvolatile memory during the battery modes can be disconcerting at first. Only GP0..GP7 and the clock
are guaranteed nonvolatile. GP0..GP7 are cleared on reset.
In particular, the meter should be designed so that the DIO pins and serial port outputs do not need to be powered in
battery modes.
The data sheet for the 71M653x shows which bits are reset, and which are maintained in the battery modes.
The transitions between the modes are managed by changes in supply voltage, transitions of the push button pin
signal, and a wake-up timer.
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