Maxim Integrated 71M6534 Energy Meter IC Family Software - Manual (Page 102)

71M653X Software User’s Guide
5.18.3 CE Data Location is at XDATA 0x0000
CE data now resides in roughly the first 1K bytes of RAM, from 0x0000 to 0x03FF. The exact CE RAM usage varies
with different CE code versions, with single-phased CE codes taking less RAM, and three-phase CE codes taking up to
the limit. Nonstandard CE codes may take more than 1K, but these will come with instructions.
Standard CE configuration begins at 0x0010. Standard CE output areas begin at 0x0200.
The Keil compiler must be configured to avoid the CE RAM. If not, both the CE code and MPU code will misbehave
when the MPU writes data into the CE code’s internal data area and vice-versa.
5.18.4 CE Data Access is Transparent to the MPU
The MPU can now simply read and write the CE RAM. No special buffering or access routines are required.
The demo code, for example, no longer copies data from the CE’s output area to the MPU RAM. The Keil C code
simply uses the CE’s output data.
It’s fast to access the CE’s output as PDATA variables, so in the demo code, the PDATA page register (SFR 0xB7) is
set to 0x200. The CE output registers begin on a page boundary, 0x200.
5.18.5 Read-only areas in MPU RAM
The direct-memory-access ADC writes automatically to XDATA locations 0x0000..0x000E, so these are not stable for
memory tests, and there is no way to disable the writes. Also 0x000F is a write-only alternate location of the chip’s
version identification.
5.18.6 CE Code Location
The 6521 also keeps CE code in flash. However the CE_LCTN register in the 653x series has 6 or 7 bits. It’s prudent
to move the CE code out of page zero. Page zero often becomes crowded with data and tables in a banked
application, and the CE code and data initialization are relatively large tables that are easy to move. It is best to place
the CE program in a high code bank so it does not compete with the MPU for flash. The demo code puts it near the
end of the last bank.
5.18.7 CE Causes Flash Write-Protection
Like the 6521, since the CE resides in flash memory, there are safeguards that prevent the CE program memory from
being erased or reprogrammed while the CE is running.
When programming flash memory from an emulator, the CE must first be disabled by writing 00 to XDATA 0x2000.
Only then, programming of the flash memory can occur.
Most practical flash write code simply disables the CE, writes the flash, and enables the CE. This is the fastest way to
write the flash, and the metering values for the disabled period can be interpolated.
Automated flash writes with the CE running are theoretically possible. The writes have to be synchronized with an
interrupt from the correct (trailing) edge of the CE_BUSY signal. Also, with three phase CE code, there is usually only
enough time to write one byte before the next CE run starts. This would confine a transparent flash write scheme to a
maximum data rate of 2520 bytes per second. If the MPU disables interrupts at all, the write can miss the window and
fail. In this case, the write can detect a failure to write by examining and clearing the FWCOL0 bit. If the FWCOL1 bit
is set, the write was in progress when the CE pass should have started. In this case, the code must count the failed
CE code passes and prorate the metering data. Prorating the metering data is unacceptable to many users.
5.18.8 Watchdog Location
The watchdog reset bit moved to bit 7 of SFR 0xF8. The other bits of this register are read-only.
5.18.9 Software Watchdog Now Deprecated
The 652x series had a software watchdog that was part of the 8051 core, and which could be disabled by software.
The 653x series no longer supports the core’s watchdog. Instead, use the standard watchdog, which cannot be
disabled by software.
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