Maxim Integrated 78Q8430 Software Driver - Manual (Page 8)

78Q8430 Software Driver Development Guidelines UG_8430_004
3 MAC Operations
This section describes the procedures to implement the following 78Q8430 MAC related operations:
• Basic transmit and receive
• Hardware Jabber protection
• Pause frame transmission with watermarking
• HNR frame transmission
• Receive interrupt delay timer
• Host
Drop
• Append and strip CRC
• Strip
padding
3.1 Basic Transmit
The basic transmit operation is achieved using the QUE 4 registers. QUE 2 is reserved for PAUSE frame
transmission, QUE 3 is reserved for high priority frames and transfer frames, and QUE 5 is reserved for
HNR frames. Use the following procedure to add a frame to QUE 4 for basic transmission:
STEP 1: Write to QUE 4 PCWR.
Writing to this register sets the ID and transmission options for the frame and initializes the write logic
for QUE 4. The driver should assign a unique ID number to each transmitted frame. When the write
logic is initialized, it triggers an under-run interrupt for QUE 4 if the previous frame has not been
completed. This has the effect of aborting the previous frame.
STEP 2: Write to QUE 4 PSZR.
Writing to PSZR indicates to the QUE 4 write logic how many bytes to expect. For example, if the
part is operating in 32-bit bus mode and the byte count is not an even multiple of four, the write logic
uses the size value to determine how many bytes in the last write are valid. If the host attempts to
write an extra word past the end of the programmed size, an overrun interrupt results.
STEP 3: Write the frame data to QUE 4 TDR.
Each successive write to TDR adds the data to QUE 4.
STEP 4: Read the transmit status from TPSR.
Reading TPSR reads status words from the top of a 128 word deep FIFO. One status word is added
to the FIFO for each transmitted frame. If the status words for transmitted frames are not read from
the FIFO, it eventually fills to capacity at which time any new status words are dropped while the
FIFO retains the oldest ones.
Use of the deferral timeout feature can cause 802.3 non-conformance. To avoid this, the disable
deferral timeout bit in the PCWR should always be set.
The software driver should retain the buffer memory containing the transmitted frame until the transmit
status for that frame has been received. The status can be associated with the buffer that contains its
data using the ID assigned in QUE 4 PCWR, which is also contained in the TPSR status word. Once the
TPSR Done bit is set and the transmit status in known to be good the driver can safely de-allocate the
buffer memory. In this way, if there was a problem during transmission and the status is not good, the
driver can resubmit the frame if needed.
The procedure above assumes that the MAC transmitter is enabled and is not halted and that the MAC
has been properly configured via the MCR.
The transmit status for a frame will not be available until the transmission completes. The driver may
need to have provisions to recover the status at a later time.
8 Rev. 1.0