Maxim Integrated 78Q8430 Software Driver - Manual (Page 13)

UG_8430_004 78Q8430 Software Driver Development Guidelines
Rev. 1.0 13
The following procedure is used to set the HNR Timer duration:
STEP 1: Write the desired HNR Timer duration to the HNRCR.
The value written is the timer duration measured in system cycles. As an example, if the system
clock is 100 MHz, then the timer is in multiples of 10 nanoseconds. In this case, the maximum timer
value of 2
32
is almost 43 seconds.
3.5.3 HNR Transmit Immediately
Use the following procedure to cause the immediate transmission of the HNR frame:
STEP 1: Read the value of the QUE 5 QSR.
STEP 2: Set the QDR bit in the QUE 5 QSR value.
This can be done using a bit-wise OR operator.
STEP 3: Write the new value back to the QUE 5 QSR.
This sets the QUE 5 QDR bit and cause the MAC transmitter to select QUE 5 for transmission of the
next frame as long as no other transmit QUEs have their QDR bit set. In other words, the HNR frame
transmits with the lowest priority.
The driver should not set the QDR bit for QUE 5 if no frame has been loaded into QUE 5.
3.6 Receive Interrupt Delay Timer
The early receive interrupt has a delay timer feature. This feature is intended to leverage the deep
receive buffer to decrease interrupt handling overhead in the host. Normally, the early receive interrupt is
triggered as soon as any data for a received frame is placed into the receive QUE. The receive interrupt
delay timer delays this interrupt for a programmable amount of time to allow the receive QUE to
accumulate more data. In this way, under conditions of heavy load, several frames can be serviced by a
single receive interrupt.
The interrupt timer is linked to the PHY speed such that the timer value is measured in byte times, or in
other words, a single tick on the interrupt delay timer is equal to the amount of time it would take the PHY
to receive a single byte. The timer does not require that an actual byte be received so the interrupt delay
feature will not cause small frames to be left in the QUE while waiting for more data. Anytime data is
added to the receive QUE and the interrupt delay timer is enabled, the timer is started if it is not already
running. If the interrupt delay timer is already running when data is added to the receive QUE, the
running timer is not affected. When a BLOCK is removed from the receive QUE, the interrupt delay timer
is reset. This means that the driver must completely empty the receive QUE each time it services the
delay timer interrupt or risk stranding data in the QUE.
If the receive QUE is empty when the interrupt timer is initially started, the maximum number of bytes that
can be in the receive QUE when the interrupt is triggered is the delay value plus 252. The driver should
therefore set the timer value based on the maximum amount of data it wants to accumulate in the QUE
before servicing it.
Use the following procedure to set the interrupt delay timer value:
STEP 1: Write the desired timer delay value to the IDCR.
The timer value is a 15-bit value.
3.7 Host Drop
The host drop feature is used by the driver to quickly remove the top frame from the receive QUE without
having to use the basic receive frame procedure in Section
3.2 . This method for dropping frames is very
efficient. A frame of 1522 bytes can be dropped from the QUE in about 12 clocks.