Maxim Integrated 78Q8430 Software Driver - Manual (Page 26)

78Q8430 Software Driver Development Guidelines UG_8430_004
STEP 2: Write the desired amount of data.
Once the slave DMA Write Mode is set, all writes on the host interface, regardless of the address,
write to the programmed TDR indicated by the Address field of the DMA register. The DMA address
is auto-incremented when the host makes successive writes to the RDR.
STEP 3: Read the DMA register to clear the Write Mode bit and terminate DMA Write Mode.
The Write Mode bit is self-clearing and any read operations on the host interface bus while in slave
DMA Write Mode clear the bit and terminate the DMA mode.
Care must be taken while the 78Q8430 is in DMA mode. If an interrupt service routine is entered
while in DMA mode, the read/write bus operations executed by the interrupt routine may not have
the desired effect. The driver software should consider using a semaphore to the ISR to indicate
the DMA mode to the ISR, or blocking all interrupts, possibly at the HIMR, before entering DMA mode.
5.2 Jumbo Frames
Normally frames in excess of the maximum size allowed by 802.3 are flagged as bad. The Jumbo Frame
feature allows these frames to be transmitted and received. This section describes the procedures for
transmitting and receiving jumbo frames.
5.2.1 Receive Jumbo
Use the following procedure to receive frames that are too large to fit into QUE 0 all at once.
STEP 1: Read the status from RPSR.
If the RPSR Done bit is set, the entire frame is already in the receive QUE and the basic receive
procedure
3.2 can be used to receive the frame.
If the RPSR Done bit is not set, follow STEPs 2 through 8 to receive the jumbo frame.
STEP 2: Allocate a memory buffer large enough to hold a maximum jumbo frame.
Since the final frame size is unknown, assume the maximum size so that the buffer will be large
enough for the entire frame. As an alternative, the driver may use any scatter/gather algorithm to
allow it to allocate multiple buffers each of the correct size for the amount of data available.
Implementation of this may depend on what the IP stack supports.
STEP 3: Read all available data from QUE 0.
Each successive read from the QUE 0 RDR removes data from QUE 0. Take care not to read extra
data. The driver must track the current position in the buffer so that when additional data is available
it is appended to the buffer at the correct location.
STEP 4: Reread the status from RPSR.
This procedure does not specify whether reading the RPSR is polling or interrupt driven. Whatever
scheme is used should be engineered to ensure that the receive buffer does not overflow between
reads of RPSR.
STEP 5: Examine the status bits in the new RPSR value.
If a fatal error has occurred in the frame since the last read of the RPSR, the Host Drop procedure,
described in Section
3.7 , can be used to discard the rest of the frame in the receive QUE and free the
buffer. This avoids unnecessarily reading data for a bad frame from the receive QUE.
STEP 6: Examine the new frame size (RPSR Count field) value.
If the new frame size is less than the amount of data already read into the buffer than the size field
has rolled over and the frame should be treated as a jabber frame and discarded.
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