Digilent Pegasus Board - Manual (Page 10)

Pegasus Reference Manual Digilent, Inc. ™
www.digilentinc.com Page 10
Tw
Th
OE
CS
WE
DB0-DB7
Th
Teoe
Tsu
Tdoe
Ten
Read data latch time
CS
Tdoe Teoe
OE
WE
Th
DB0-DB7
Tsu
Write Cycle
Read Cycle
Th
Th Ten
Twd
ASTB
DATA
T
SU
Write Cycle*
Read Cycle*
T
STB
DSTB
WAIT
nWR
T
WT
T
WR
T
STB
* ASTB and DSTB determine whether an address or
data write cycle occurs. Only one should be
asserted for each bus transaction.
Th
ASTB
DATA
Tsu
T
STB
DSTB
WAIT
nWR
T
WT
T
WR
T
STB
T
H
T
H
T
H
T
H
T
H
System Bus Timing
Symb
ol
Parameter Time
(typ)
ten Time to enable after CS asserted 10ns
th Hold time 1ns
tdoe Time to disable after OE de-
asserted 10ns
teoe Time to enable after OE asserted 15ns
tw Write strobe time 10ns
tsu Data setup time 5ns
twd Write disable time 0ns
Module Bus Timing
Symb
ol
Parameter Time
(typ)
tstb Strobe time 10ns
twt Strobe to wait time 10 ns
twr Time to enable write 15 ns
tsu Data setup time 5 ns
th Data hold time 5 ns
Figure 14. Peripheral bus signals and timings