Digilent Parallel Interface Model - Manual (Page 2)

Digilent Parallel Interface Model Digilent, Inc.
www.digilentinc.com Copyright Digilent, Inc. Page 2
ASTB host Address strobe. Causes data to be read or written to the address
register
DSTB host Data strobe. Causes data to be read or written to a data register
WAIT peripheral Synchronization signal used to indicate when the peripheral is
read to accept data or has data available.
INT peripheral Interrupt. Used by the peripheral to interrupt the host to request
service. Not used by all Digilent communications subsystems.
RESET host Reset. Allows host to reset logic in the peripheral. Not currently
used by all Digilent communications subsystems.
Transfers from the host to the peripheral or from the peripheral to the host are accomplished using
one of four transfer bus cycles. The four possible bus cycles are: Address Read, Address Write, Data
Read, Data Write. The direction of the data transfer is controlled by the WRITE signal. If WRITE is
high (indicating a READ cycle) the peripheral is the source of the data and drives its data onto the
bidirectional data bus at the appropriate time in the cycle. If WRITE is low (indicating a WRITE cycle)
the host is the source of the data and drives its data onto the bidirectional data bus. It is extremely
important that the peripheral logic in the gate array not drive data onto the data bus except during a
READ cycle. If the data bus is driven by the peripheral at incorrect times, it is possible to create bus
contention that can damage either the gate array or the communications subsystem. All bus cycles
are initiated and controlled by the host.
The WAIT signal is used to synchronize transfers between the host and the peripheral. The host will
not begin a transfer unless the wait signal is low. Once the host begins a bus cycle, it will hold the
strobe (either ASTB or DSTB) in the active state (prolonging the bus cycle) until WAIT goes high.
WAIT going high signals that the peripheral has completed its processing of the cycle. The host will
then bring the strobe to the inactive state completing the bus cycle. The peripheral then brings WAIT
low when it is ready for another transfer to begin.
Timing Diagrams
The following diagrams illustrate the signal timing for the various transfer cycles. For write
cycles, the rising edge of the strobe signal (ASTB or DSTB) is the active edge and causes
the data to be latched into the register in the gate array. For read cycles, the WRITE signal
and the appropriate strobe are combined to enable to bus buffers to drive data onto the bus
when it is a read cycle and the strobe is active.
WAIT must be in the inactive state (low) before the communications module will start a
transfer cycle. The communications module will not complete a transfer cycle until WAIT goes
high. The gate array logic may delay bringing WAIT high to until data is available if
necessary. However, if WAIT is not brought high within approximately 10ms of the start of a
transfer, the communications module will abort the transfer and report a time out error back to
the host. Similarly if WAIT does not come low to allow a transfer to begin within
approximately 10ms, the communications module will report a time out error to the host.