Fluke 900 - Manual (Page 34)

Seiftest FLUKE 900 SERVICE MANUAL
The bits in the tesults indicate nonnal pin numbers with the exception of the following:
BYTE 0 - B7 - NAJ
B6- N/U
B5 - Could not clear PAL latches.
B4 - Could not activate aU lines with a single edge.
TESTS 42 43
PULLO_ACT_TSTON, PULL1_ACT_TSTON
These tests walk a rising edge(l) or a falling edge(0) horn the puU-iq>s latches through the
activity circuitiy. The activity circuit is controlled by the TSTON signal.
TESTS 44, 45
PULLO_ACT_ACTSTR, PULL1_ACT_ACTSTR
These tests walk a rising edge(l) or a falling edge(0) fiom the pull-ups latches through the
activity circuitry. The activity circuit is controlled by die ACTSTR signal.
TESTS 46,47
freq _ bias _ short , freq _ bias _ long
These two tests are almost identical, the only difference being that the long test verifies aU
possible values of threshold and the short test only tests at 1 volt increments. The tests are a
collection of several subtests involving frequency and threshold hardware on the High Speed
Board and Input Buffer and they are detiuled below. As they are being done, the left part of
the screen shows timing values from the frequency test and the right side of the screen shows
the highest and lowest differences between expected and measured voltage values.
Many of the subtests require that a voltage on the Interface Buffer be measured. One of
several possible voltages is selected using the analog mux on the input buffer. This feeds the
into the VCO, the output of which is sent to the High Speed Board where the frequency is
measured. The same thing is also done for 0 volts and 2.5 volts to obtain a calibration ratio
that is used to determine the exact voltage of the signal selected.
Interface Buffer shift register subtest
This tests to see if data can be shifted through the shift registers on the Interface Buffer
correctly. There are two banks of registers on the board. Only the puUup registers are
explicitly tested because there is no feedback line from the threshold registers. The
threshold registers are implicitly tested by the other tests. The test procedure is as follows:
a) shift data - msbit = 0
b) read the voltage of the msbit: must be <2V
c) shift data - msbit = 1
d) read the voltage of the msbit: must be >2V
3 - 1 0