Fluke 900 - Manual (Page 22)

Theory of Operation FLUKE 900 SERVICE MANUAL
12. Trig Data Latch
The shift register latches U166, U189, UlOO, U78 are loaded with data indicating Is
and Os of the Trigger word. The first word is serial shifted and latched followed by
the second word which is not latched until the occurrence of the first.
13. Trig Qual Latch
The shift register latches at U168, U188, U96, US6 are loaded with data indicating
which pins have a 1 or 0 and which have "don’t care" conditions. Two successive
words are loaded as in the Trig Data case.
14. Activity Circuit
This circuit on page 7 of the Micro Board schematics operates by latching the state
of all pins at the start of test and generating an exclusive OR pulse if the state ever
changes, hi this way, the PALs U32, U21, U16, U22 are alerted of active pins.
15. Mon Bus Readback
The Mon Bus which comes from the ffigh Speed Board to the Micro Board via the
connector J3 is shown on page 13 of the MB schematics. The latches and PALs on
page 7 use the Mon Bus to hold the state of all pins at the end of test (for the EoT
test result). The state of pins at the start of test is also latched here for the purpose
of checking H or L conditions on DUT pins.
16,18. Shadow Ram and Delayed Gate Circuit
This circuit is implemented in the Logic CeU Array at U123 (page 6) and associated
PALs. Both of these functions affect the gating of comparison. Shadow RAM
inhibits comparison during reading of an uninitialized DUT memory cell. Delayed
gate inhibits the normal gate signal from going true for a fixed time interval after its
pin conditions are satisfied.
17. RD Emulation Circuit
This Logic Cell Array, located at U105 (page 12), simulates certain Reference
Devices instead of using an RD in the socket. If an H3 Board does not have the
Simulation Option instafied, U105 is still present to perform selftest functions.
Test cycle control is applied to all 28 channels together and is found on page 3 of the H3
schematics. The Time CIO at U26 is configured so РАО, 1,2 enable the Trigger flip flops and
GATE PAL. РАЗ is an output for enabling comparison during selftest. PA4 is an input that
detects whether gate occurred. PA5 is an input indicating a short in the RD socket. PA6, 7 are
inputs that detect whether trigger word 1 and 2 occurred.
Port В controls the Test Cycle PAL; PBl is an input which stops test after a fault has been
captured. PB2, 3, 4, 5 are inputs from a counter which acts as a prescaler for the time-to-fault
interval. An internal CIO timer converts it to a value in the proper range. PB6 is an output that
clears the fault under CPU control, while PB7 is an input indicating a fault is present Port C is
configured as an output and it selects which shift register will receive the data stream from the
register U36 on page 1 of the H3 schematics.
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