Fluke 2180A - Manual (Page 29)

2180A
When 0.01° resolution is in use, Q12 will allow reference
capacitor C19 to attain a -100 mV charge. For 0.1°
resolution, Q8 will allow C20 to charge to ° l.OV. Either
reference capacitor will be placed at the -Sense level
during Auto-Zero. Recovery deintegrate is applied to
QIO and Q14.
3-23. A second voltage reference (U15-6) provides an
accurate 6.2V across the series combination of R1 (Main
Thermometer PCB), R2 (RTD Input PCB), and the
RTD. This voltage therefore provides the source (+V)
voltage for the RTD.
3-24. The Buffer, Integrator, Gain Stage, and
Comparator Amplifiers combine to perform the analog
functions of the Integrate, Read, and Auto-Zero periods.
The Buffer is used to provide integrator inputs during all
three periods. The Integrator integrates the Buffer output
voltage during the Integrate and Read periods and, in
combination with the Gain Stage, functions as a closed-
loop amplifier during the Auto-Zero period.
3-25. An Auto-Zero period is commanded during the
first phase of each measurement cycle. During this time,
five auto-zero switches (Q4, Q5, Q11, Q15, and Q22) are
closed by the microcomputer. Three of the switches (Q11,
Q15, and Q22) charge the reference capacitors to +100
mV on Cl9 and +1.0V on C20. Closing switch Q4
connects the Integrator and Gain Stage into a closed-loop
configuration. This action also allows the Auto-Zero
capacitor (Cl2) to charge to a value proportional to the
algebraic sum of all the offset voltages in the Buffer,
Integrator and Gain Stage. At the end of the Auto-Zero
period, switches Q4, Q5, Q11, Q15, and Q22 are opened.
The reference capacitors (Cl9 and C20) and the Auto-
Zero capacitor retain their charges for later use in the
measurement cycle.
3-26. The Integrate period (see Figure 4-4) starts on the
leading edge of the integrate command from the
microcomputer; switch Q21 is closed and switch Q7 is
opened. The RTD input voltage is applied through switch
Q21 to the Buffer input. After a 1 ms settling period,
switch Q7 closes, and the Buffer output is applied to the
Integrator for 100 ms. As the integrator capacitor C2
charges, the Integrator drives the comparator, through
the gain stage to +5V dc which indicates that the charge
on C2 is more negative than the Auto-Zero Reference
Cl2. At the end of the Integrate period, the integrate
capacitor is charged to a level and polarity proportional
to the RTD voltage, and switches Q21 and Q7 return to
the open state.
3-27. The Read period starts at the end of the Integrate
period. Depending upon the input polarity sensed by the
comparator during the Integrate period, one of two Read
modes is enabled if a positive input is sensed, a positive
Read mode is enabled. Similarly, a negative Read mode is
enabled when a negative input is sensed.
3-28. When the positive Read mode is commanded,
FET switches Q13 and Q9 are closed. If 0.1° resolution is
in effect, Q8 will place the positive side of reference
capacitor C20 at ground. With 0.01° resolution in effect,
Q12 will place the positive side of reference capacitor Cl 9
at ground. Reference capacitors C20 and Cl9 will then
apply either -1 .OV or -100 mV, respectively, to the Buffer
input.
3-29. When the negative Read mode is commanded,
switches QIO and Q14 are closed; Q9 and Q13 are open.
With .01° resolution selected, approximately +200 mV
will be applied to the positive side of reference capacitor
Cl9. The algebraic sum of the voltage at the Buffer input
will then be +100 mV. When 0.1° resolution is selected,
approximately +2.0V will be applied to the positive side
of reference capacitor C20. Buffer input voltage will then
be +1.0V (only during recover deintegrate).
3-30. After a 1 ms settling time, switch Q7 closes and the
Buffer output voltage is applied to the Integrator input.
The integrator capacitor now begins to discharge at a
linear rate (determined by the reference voltage). This
discharge continues until the integrator voltage reaches
the comparator trip point, which is referenced to the
voltage on the Auto-Zero capacitor. When this level is
reached, the comparator changes state, commanding the
microcomputer to terminate the Read period. To
facilitate auto-zero, the microcomputer then calls a
reference voltage opposite in polarity to the one
previously used (DE- or DE+). When the integrator
reaches the trip point, the microcomputer immediately
begins the Auto-Zero period.
3-31. Offset voltages present during the Integrate and
Read periods are cancelled by offset voltages that were
sampled and held during the Auto-Zero period.
3-32. POWER SUPPLY
3-33. The 2190A Power Supply consists of a DC to DC
Converter and regulating circuitry. AC inputs are made
via the input power cord, line fuse, and power
transformer/rectifier. External +12V dc inputs can also
be made directly to the DC to DC Converter circuitry via
line TBl (see Main PCB schematic. Section 8). The
function of the power supply is to provide +5V, +5V
unregulated, +15V, and -15V dc operating voltages for
the 2180A circuitry. The power supply can be driven from
ac line or 12V dc external source. The DC to DC
conversion and voltage regulation is accomplished using
conventional power supply design techniques.
3-5/3-6