Fluke 2180A - Manual (Page 27)

2180A
AOU/DOU
OPTION
LIMITS
OPTION
ri__rt
Q22
05 04 015 Oil
( ^ © © © ©
021 ( k
CO
I
CJ
CO
h-
LU
Q7 k
AZ
INTI
A2
016 k
X10
017 ( k
XI00
Q10{ k
014 (k
-
DE-
013 ( k
Q9 k
DE+
MICRO­
COMPUTER
U9
>
<
T ^
f^o
MHz
U16
Figure 3-2. Simplified Schematic — Digital
A/D Converter (integrator, gain stage, and comparator),
and a combination of FET switches. Refer to Figure 3-3
in conjunction with the following individual circuit
descriptions. All FET switches will be shown in their open
state; they are closed during measurement cycle
commands from the 2180A’s digital section.
3-19. The RTD Input circuit comprises the RTD probe,
the RTD Input Module, and a low pass filter on the Input
Module’s PCB. Source current flows through a series
combination of the RTD probe, R2 (RTD Input
Module), and R1 (Main PCB). The voltage sensed across
the RTD is routed through the Input Module, and onto
the Main PCB. The TSense line (always a positive
voltage) is then applied to the low pass filter.
3-20. The ground sense amplifier (Q20, U7 and
associated circuitry) maintains the -Sense line at
measurement ground. This amplifier compensates for
noise and offsets on the -V and -Sense lines.
3-21. To achieve switching between 0.01° and .1°
resolution, the buffer gain is shifted by a factor of ten. For
0.01° resolution, FET switch Q17 is on, and a reference
voltage of-100 mV is applied to the buffer (Q19, U5). The
buffer gain is set to 100. For 0.1° resolution, FET switch
Q16 is on, and a reference voltage of -1 .OOV is applied and
the buffer gain is 10.
3-22. The first voltage reference consists of a resistor
network supplied by an accurate 6.2V dc reference
voltage. The resistive divider network is set to provide 200
mV to Q14, lOOmVtoQ15, l.OVtoQl l,and2.0VtoQlO.
3-3