Pioneer PDR-04 - Manual (Page 73)

PDR-04
Pin No. Mark Name I/O Initial Function
41 P33/SI/SBI MSI 1 L Clock sync serial transfer data input
42 P34/SCK“" MSCK 0 H Clock sync serial transfer clock output
43 NC GND - - Not used
44 P80/T000 XFUSE 1 H "L" when communication between LC89585 <=> Mode contoroller
45 P81/T001 GFS 1 - GFS input ("H" when GFS OK)
46 P82/T002 ECLV 0 H Spindle servo EFM/Wobble CLV mode
47 P83/T003 CLV o H Spindle servo CLV/CAV mode
48 P84/T010 SPSQ 0 - Spindle drive PWM output during spindle CAV
49 P85/T001 MREQ 0 H "L" when opposite mode controller serial handshake Is output
50 RESET"“ XRST 1 - "L" when reset input
51 XI CLOCK 1 - System clock oscillation crystal connection pin
Input to XI pin when clock is supplied from outside 52 X2 CLOCK - -
53 NC GND -
- Not used
54 Vss GND -
- GND pin
55 WDTO“” NC o L Not used
56 POO/RTPO XSUBQE 0 H "L" when EFM decoder sub code Q reading is enabled
57 NC GND - - Not used
58 P01/RTP1 XENCE 0 L "H" when LC89585 serial enable is output
59 P02/RTP2 XASYN 0 L ATIP frame sync "L"
60 P03/RTP3 XEXSC 0 H "L" when LC89585 external sync enable is output
61 P04/RTP4 SSO 0 L SONY servo 1C command special serial data output
62 P05/RTP5 SSCK 0 H SONY servo 1C command special serial clock output
63 P06/RTP6 XLT 0 H "L" when SONY servo 1C command is latched
64 P07/RTP7 RECE 0 L “H" when laser diode recording power is on
65 EA“"A/pp EA~ 1 - Used as internal ROM mode when connected to +5V
66 Vss GND - - GND pin
67 P93/TMD RAME 0 H "H" when external SRAM is enable
68 P92/TAS~ XSVRST 0 L "L" when servo system 1C mode control reset is output
69 POI/WR“ XWR 0 L Strobe signal output for external memory write operations
70 P90/RD“ XRD 0 L Strobe signal output for external memory read operations
71 ASTB ASTB o - Signal which latches lower address signal for external memory access externally
72 P40/ADD ADO I/O —
Data address line 73 P41/AD1 ADI I/O -
74 P42/AD2 AD2 I/O -
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