Kontron SMARC Evaluation Carrier - Manual (Page 32)

User’s Guide
32 www.kontron.com
7.7 Jumper J59 – Carrier Dual Channel LVDS Clock Edge
A 24 bit dual channel LVDS implementation comprises 10 differential pairs: 4 pairs for odd pixel and control data; 1 pair
for the LVDS clock for the odd data; 4 pairs for the even pixel data and control data, and 1 pair for the even LVDS clock.
The SMARC Evaluation Carrier uses one LVDS transmitter for even pixel signals (U14) and another LVDS transmitter for
odd pixel signals (U21). Data is clocked into the pair of Carrier Board LVDS transmitters by LCD_DUAL_PCK.
J59 is used for selecting the active clock edge for the LVDS transmitters to latch data on as shown below:
Jumper Position Function
J59
Inserted
U14 latches on rising clock edge and U21 latches on falling clock
edge
Not inserted
U21 latches on rising clock edge and U14 latches on falling clock
edge
7.8 Jumper J60 – Carrier LVDS Pixel Clock Rate
J60 is a 3 pin header. Two pins (1-2 or 2-3) are shorted together to select between two pixel clock options. For dual-
channel LVDS displays connected to the Carrier KLAS board, use the 1-2 position. For single channel displays, used the
2-3 position.
Jumper Position Function
60
1-2 Dual Pixel Clock (one- half frequency of Pixel Clock)
2-3 Pixel Clock
7.9 Jumper J51 and J53 – Battery Select – Power Paths
Three batteries (BAT1, BAT2 and BAT3) are provided on the board and the user can realize various combinations
mentioned in the table below based on the position of the jumpers J51 and J53.
Function Inserted Not inserted
3.6V Li-Ion (1 cell, BAT1) J51 (Pin 3-4) All others
3.6V Li-Ion (2 cells, parallel, BAT1 & BAT2)
J51 (Pin 1-2)
J51 (Pin 3-4)
J53 (Pin 3-4)
All others
7.2V Li-Ion (2 cells, series, BAT1 & BAT2)
J51 (Pin 2-3)
J53 (Pin 3-4)
All others
10.8V Li-Ion (3 cells, series BAT1, BAT2, &
BAT3)
J51 (Pin 2-3)
J53 (Pin 2-3)
All others