Kontron COMe-cPV2(v1.0) - Manual (Page 50)

Kontron microETXexpress-PV User’s Guide
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The implementation of this subsystem complies with the COM Express®
specification. For additional implementation information, refer to the PICMG
COM Express® Design Guide on the PICMG website.
In compliance with the EN60950 standard, there are at least two current-
limiting devices (resistor and diode) between the battery and the consuming
component.
NOTE: A diode and resistor protection is already present on the module.
I
2
C Bus
The I²C bus is implemented using bit banging. The speed for this bus is
always 100kHz. No multi-master support is available.
See the Chapter 8, “BIOS Operation” for supported I 2 C features.
SMBus
System Management Bus (SMB) signals are connected to the SMBus controller,
which is located on the Intel® ICH8M. The SMBus is a 2-wire bi-directional
bus (clock and serial data) used for system management tasks such as reading
parameters from a memory card or reading temperatures and voltages of system
components.
The SMBus uses the same signaling scheme as the I 2 C bus.
PCI Bus
The processor provides a standard PCI 2.3 32-bit/33 MHz interface. The
implementation of this subsystem complies with the COM Express®
Specification. For additional implementation information, refer to the PICMG
COM Express® Design Guide.
WARNING: The following signal is not 5V tolerant as required by the COM
Express 2.0 specification:
- Pin D48 - PCI_CLKRUN#
IDE Port
The IDE host adapter on the Intel® ICH8M supports PATA/UDMA-33/66/100
operation. The implementation of this subsystem complies with the COM
Express® Specification. For additional implementation information, refer to
the PICMG COM Express® Design Guide on the PICMG website.