Cirrus Logic EP7312 - Manual (Page 31)

DS508F2

Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 31
EP7312
High-Performance, Low-Power System on Chip
208-Pin LQFP Pin Diagram
Note: 1. N/C should not be grounded but left as no connects.
160
159
158
157
53
54
55
56
57
58
59
60
61
62
63
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
10
6
10
7
10
8
10
9
11
0
11
2
11
3
11
4
11
5
11
6
11
7
11
8
11
9
12
0
12
1
64
65
67
68
69
70
71
72
73
74
75
66
98
99
100
101
102
103
104
12
2
12
4
12
5
12
6
12
7
12
8
12
9
13
0
10
5
13
1
13
2
13
3
13
4
15
6
15
5
15
4
15
3
15
2
15
1
15
0
14
9
14
8
14
7
14
6
14
5
14
4
14
3
14
0
13
9
13
8
13
7
13
6
14
1
14
2
13
5
161
162
163
164
165
166
167
168
169
170
171
172
173
174
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
201
202
203
204
205
206
207
208
200
175
176
177
178
179
12
3
11
1
EP7312
208-Pin LQFP
(Top View)
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 50 52 1
nEX
T
PW
R
BA
T
O
K
nP
O
R
VSSOSC
VDDOSC
MOSCIN
MOSCOUT
nU
RESET
WAKEUP
A[6]
D[6]
A[5]
D[5]
VDDIO
VSSIO
A[4]
D[4]
A[3]
D[3]
nPWRFL
A[2]
D[2]
A[1]
A[0]
D[0]
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
FRM
M
DD[2]
DD[1]
DD[0]
nSDCS[1]
SDQM[3]
SDQM[2]
VDDIO
VSSIO
SDCLK
nMWE/nSDWE
nMOE/nSDCAS
nCS[0]
nCS[1]
nCS[2]
nCS[3]
D[
7]
A[7
]
D[
8]
A[8
]
D[
9]
D[
10
]
A
[10]
VSSIO VDD
IO
A
[11]
D[
12
]
A
[12]
D[
13
]
A[1
3
]\DR
A
[1
4]
D[
14
]
DD[3]
D[
17
]
D[
15
]
A
[17]
/D
R
A
[10]
nT
R
S
T
VSSIO VDD
IO
D[
18
]
A[1
8
/D
R
A
[9
]
D[
19
]
A
[19]
/DRA[
8
]
D[
20
]
VSSIO A
[21]
/DRA[
6
]
D[
22
]
D[
23
]
A
[23]
/DRA[
4
]
D[
24
]
VSSIO VDD
IO
A
[24]
/DRA[
3
]
HAL
F
WO
RD
A[1
4
]/DR
A
[1
3]
n
BATCHG
A[25]/DRA[2]
D[25]
D[27]
A[27]/DRA[0]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]
ADCOUT
ADCCLK
DRIVE[0]
VDDIO
PD[2]
VSSIO
VSSCORE
nADCCS
ADCIN
SSIRXDA
SSIRXFR
SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]
PD[3]
A
[22]
/DRA[
5
]
PD[4]
VDDIO
PD[5]
PD[6]/SDQM[0]
DRIVE[1]
PD[7]/SDQM[1]
D[26]
A
[15]
/D
R
A
[12]
D[
16
]
A
[16]
/D
R
A
[11]
nCS[4]
VDDCORE
A[26]/DRA[1]
D[
21
]
TMS
A
[20]
/DRA[
7
]
SMPCLK
D[
11
]
A[9
]
D[1]
VSSCORE
nSDCS[0]
SDCKE
VSSIO
VSSIO
VSSIO
VSSIO
EXPCL
K
WO
RD
WR
IT
E/nS
DR
AS
RU
N/
C
L
K
E
N
EXP
RD
Y
PB
[7
]
PB
[6
]
PB
[5
]
PB
[4
]
PB
[3
]
PB
[2
]
PB[
1]
VSSIO
TD
I
VD
DIO TD
O
PE[2
]/C
LKSEL
n
EXTF
IQ
PA[
6]
PA[
5]
PA
[4
]
PA[
3]
PA[
2]
PA[
1]
PA[
0]
L
E
DD
RV
TXD
[2
]
PHD
IN
CT
S
RXD[
2]
DCD DSR
RT
CO
UT
RT
CI
N
VSS
IO
PA[
7]
VDDI
O
VSSIO nCS
[5]
PB[
0]
TXD
[1
]
RX
D
[1
]
nTEST[1
]
nTEST[0
]
EI
NT[3
]
nE
IN
T[
2]
nE
IN
T[
1]
P
E
[1
]BOO
TSEL
[1
]
P
E
[0
]BOO
TSEL
[0
]
N/
C
VSSRTC VD
DRT
C
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
n
M
EDCH
G/n
B
RO
M