Static memory – Cirrus Logic EP7312 User Manual
Page 21
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
21
EP7312
High-Performance, Low-Power System on Chip
Static Memory
through
define the timings associated with all phases of the Static Memory. The following table contains the
values for the timings of each of the Static Memory modes.
Parameter
Symbol
Min
Typ
Max
Unit
EXPCLK rising edge to nCS assert delay time
t
CSd
2
8
20
ns
EXPCLK falling edge to nCS deassert hold time
t
CSh
2
7
20
ns
EXPCLK rising edge to A assert delay time
t
Ad
4
9
16
ns
EXPCLK falling edge to A deassert hold time
t
Ah
3
10
19
ns
EXPCLK rising edge to nMWE assert delay time
t
MWd
3
6
10
ns
EXPCLK rising edge to nMWE deassert hold time
t
MWh
3
6
10
ns
EXPCLK falling edge to nMOE assert delay time
t
MOEd
3
7
10
ns
EXPCLK falling edge to nMOE deassert hold time
t
MOEh
2
7
10
ns
EXPCLK falling edge to HALFWORD deassert delay time
t
HWd
2
8
20
ns
EXPCLK falling edge to WORD assert delay time
t
WDd
2
8
16
ns
EXPCLK rising edge to data valid delay time
t
Dv
8
13
21
ns
EXPCLK falling edge to data invalid delay time
t
Dnv
6
15
30
ns
Data setup to EXPCLK falling edge time
t
Ds
-
-
1
ns
EXPCLK falling edge to data hold time
t
Dh
-
-
3
ns
EXPCLK rising edge to WRITE assert delay time
t
WRd
5
11
23
ns
EXPREADY setup to EXPCLK falling edge time
t
EXs
-
-
0
ns
EXPCLK falling edge to EXPREADY hold time
t
EXh
-
-
0
ns