Cirrus Logic CS8421 - Manual (Page 17)

DS641F6 17
CS8421 CS8421
4.2 Mode Selection
The CS8421 uses the resistors attached to the MS_SEL, SAIF, and SAOF pins to determine the modes of operation.
After reset, the resistor value and condition (VL or GND) are sensed. This operation will take approximately 4
s to
complete. The SRC_UNLOCK pin will remain high and the SDOUT pin will be muted until the mode detection se-
quence has completed. After this, if all clocks are stable, SRC_UNLOCK will be brought low when audio output is
valid and normal operation will occur.
Tables 1 , 2 , and 3 show the pin functions and their corresponding settings. If
the 1.0 k
 option is selected for MS_SEL, SAIF, or SAOF, the resistor connected to that pin may be replaced by a
direct connection to VL or GND as appropriate.
The resistor attached to each mode-selection pin should be placed physically close to the CS8421. The end of the
resistor not connected to the mode selection pins should be connected as close as possible to VL and GND to min-
imize noise.
Tables 1 , 2 , and 3 show the pin functions and their corresponding settings.
I/OLRCK
I/OSCLK
M S B L S B M S B L S B
Channel A
SDIN
SDOUT
MSB
Channel B
Figure 7. Serial Audio Interface Format - I²S
M S B L S B M S B L S B MSB
I/OLRCK
I/OSCLK
SDIN
SDOUT
Channel A Channel B
Figure 8. Serial Audio Interface Format - Left-Justified
I/OLRCK
I/OSCLK
Channel A
SDIN
Channel B
MSB SDOUT
MSB MSB
MSB LSB
LSB
LSB
LSB
MSB Extended MSB Extended
Figure 9. Serial Audio Interface Format - Right-Justified