Cirrus Logic CS8421 - Manual (Page 12)

12 DS641F6
CS8421
DIGITAL INPUT CHARACTERISTICS
DIGITAL INTERFACE SPECIFICATIONS
(GND = 0 V; all voltages with respect to 0 V.)
SWITCHING SPECIFICATIONS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
Parameters Symbol Min Typ Max Units
Input Leakage Current I
in
- - ±10
A
Input Capacitance I
in
- 8 - pF
Input Hysteresis - 250 - mV
Parameters Symbol Min Max Units
High-Level Output Voltage, except MCLK_OUT and SDOUT (I
OH
=-4 mA) V
OH
0.77xVL - V
Low-Level Output Voltage, except MCLK_OUT and SDOUT (I
OL
=4 mA) V
OL
- .6 V
High-Level Output Voltage, MCLK_OUT (I
OH
=-6 mA) V
OH
0.77xVL - V
Low-Level Output Voltage, MCLK_OUT (I
OL
=6 mA) V
OL
- .6 V
High-Level Output Voltage, SDOUT (I
OH
=-8 mA) V
OH
0.77xVL - V
Low-Level Output Voltage, SDOUT (I
OL
=8 mA) V
OL
- .65 V
High-Level Input Voltage V
IH
0.6xVL VL+0.3 V
Low-Level Input Voltage V
IL
-0.3 0.8 V
Parameters Symbol Min Max Units
RST pin Low Pulse Width (Note 6) 1 - ms
XTI Frequency (Note 7) Crystal
Digital Clock Source
16.384
1.024
27.000
27.000 MHz
MHz
XTI Pulse Width High/Low 14.8 - ns
MCLK_OUT Duty Cycle 45 55 %
Slave Mode
I/OSCLK Frequency - 24.576 MHz
OLRCK High Time (Note 8) t
lrckh
326 - ns
I/OSCLK High Time t
sckh
9 - ns
I/OSCLK Low Time t
sckl
9 - ns
I/OLRCK Edge to I/OSCLK Rising t
lcks
6 - ns
OLRCK Rising Edge to OSCLK Rising Edge (TDM) t
fss
5 - ns
I/OSCLK Rising Edge to I/OLRCK Edge t
lckd
5 - ns
OSCLK Rising Edge to OLRCK Falling Edge (TDM) t
fsh
5 - ns
OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid t
dpd
- 18 ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge t
ds
3.5 - ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge t
dh
5 - ns