Cirrus Logic CS5566 - Manual (Page 25)

CS5566
DS806PP2 25
5/4/09
3.12 Power Supplies & Grounding
The CS5566 can be configured to operate with its analog supply operating from 5V, or with its analog sup-
plies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or
3.3V.
Figure 8 on page 18 illustrates the device configured to operate from ±2.5V analog. Figure 9 on page 19
illustrates the device configured to operate from 5V analog. Note that the schematic indicates a 47
μF ca-
pacitor between V1+ and V1-. This capacitor is necessary to reduce the peak current required from the
power supply during conversion. See
Power Consumption on page 16 for a more detailed discussion.
To maximize converter performance, the analog ground and the logic ground for the converter should be
connected at the converter. In the dual analog supply configuration, the analog ground for the ±2.5V sup-
plies should be connected to the VLR pin at the converter with the converter placed entirely over the an-
alog ground plane.
In the single analog supply configuration (+5V), the ground for the +5V supply should be directly tied to
the VLR pin of the converter with the converter placed entirely over the analog ground plane. Refer to
Figure 9 on page 19.
3.13 Using the CS5566 in Multiplexing Applications
The actual conversion process inside the CS5566 begins 1182 MCLK cycles after the CONV signal is tak-
en low. This would be over 147 microseconds when MCLK = 8 MHz. If the input channel of an external
multiplexer is changed coincident with CONV going low, the 1182 MCLK delay should be more than an
adequate time for settling. If there is an operational amplifier between the multiplexer and the converter,
one should be certain that the amplifier can settle within the 1182 MCLK delay period. If not, the multiplex-
er will need to be switched some time prior to CONV going low.
3.14 Synchronizing Multiple Converters
Many measurement systems have multiple converters that need to operate synchronously. The convert-
ers should all be driven from the same master clock. In this configuration, the converters will convert syn-
chronously if the same CONV signal is used to drive all the converters, and CONV falls on a falling edge
of MCLK. If CONV is held low continuously, reset (RST) can be used to synchronize multiple converters
if RST is released on a falling edge of MCLK.