Cirrus Logic CS5566 - Manual (Page 15)

CS5566
DS806PP2 15
5/4/09
3.2 Power Consumption
The power consumption of the CS5566 converter is a function of the conversion rate. Figure 6 illustrates
the typical power consumption of the converter when operating from either MCLK = 8 MHz or
MCLK = 4 MHz. The rate at which conversions are performed directly affects the power consumption.
When the converter is powered but not converting, it is in an idle state where its power consumption is
about 11 mW. When the CONV signal goes low to start a conversion, the converter delays the actual start
of conversion for 1182 to 1186 MCLK cycles, depending upon how CONV is controlled. The timing for the
conversion sequence is shown in
Figure 1 on page 6. After the 1182 - 1186 MCLK delay from when
CONV goes low, the converter enters a higher-power state for 354 MCLK cycles and then returns to a
lower-power state for 64 MCLK cycles, after which the RDY signal falls to indicate the completion of a
conversion. Since the peak operating current for the converter occurs during the 354 MCLK, higher-pow-
er state, it is recommended that a large capacitor be used on the supply to the converter (as shown in
Figures 9 and 10). This capacitor filters the peak current demand from the power supply. The average
power consumption for the converter will depend upon the frequency of MCLK and the rate at which con-
versions are performed as illustrated in
Figure 1 on page 6.
Figure 6. Power Consumption vs. Conversion Rate
7.5
10
12.5
15
17.5
20
0 500 1k 1.5 2k 2.5k 3k 3.5k 4k 4.5k 5k
Word Rate (Sps)
P
o
w
e
r
C
ons
u
m
p
ti
on
(m
W
)
MCLK = 8MHz
MCLK = 4MHz