Cirrus Logic CS5566 - Manual (Page 10)

CS5566
10 DS806PP2
5/4/09
DIGITAL CHARACTERISTICS
T
A = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V
DIGITAL FILTER CHARACTERISTICS
T
A = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V
16. See Figure 4 to understand conversion timing. The 160 MCLK group delay occurs during the 354 MCLK high-power period of a
conversion cycle. See Section 3.2 Power Consumption for more detail.
Parameter Symbol Min Typ Max Unit
Input Leakage Current I
in
- - 2 µA
Digital Input Pin Capacitance C
in
- 3 - pF
Digital Output Pin Capacitance C
out
- 3 - pF
MCLK
SCLK(i)
SDO
CS
RDY
LSB MSB
t
19
t
18
t
20
t
17
t
15
t
21
Figure 5. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale)
Parameter Symbol Min Typ Max Unit
Group Delay (Note 16) - - 160 - MCLKs