Cirrus Logic CS4382 - Manual (Page 37)

DS514F2 37
CS4382
9. DIAGRAMS
LRCK
SCLK
Left Channel Right Channel
SDINx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 MSB LSB MSB LSB
Figure 33. Format 0 - Left Justified up to 24-bit Data
LRCK
SCLK
Left Channel Right Channel
SDINx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 MSB MSB LSB LSB
Figure 34. Format 1 - I²S up to 24-bit Data
LRCK
SCLK
Left Channel
Right Channel
SDINx 6 5 4 3 2 1 0 9 8 7 15 14 13 12 11 10 6 5 4 3 2 1 0 9 8 7 15 14 13 12 11 10
32 clocks
Figure 35. Format 2 - Right Justified 16-bit Data
LRCK
SCLK
Left Channel
SDINx 6 5 4 3 2 1 0 7 23 22 21 20 19 18 6 5 4 3 2 1 0 7 23 22 21 20 19 18
32 clocks
0
Right Channel
Figure 36. Format 3 - Right Justified 24-bit Data